Chen Xiang, Zhao Ming, Zhao Juntao, C. Jianwen, Wang Jing
{"title":"基于CELL宽带引擎的WiMAX系统高性能信道解码器","authors":"Chen Xiang, Zhao Ming, Zhao Juntao, C. Jianwen, Wang Jing","doi":"10.1234/MJEE.V5I1.377","DOIUrl":null,"url":null,"abstract":"Wireless baseband processing, which is characterized by high computational complexity and high data throughput, is regarded as the most challenging issue for software radio (SR) systems, especially for the General Purpose Processor (GPP)-based SR systems. To overcome this implementation difficulty in SR systems, the multicore architecture has been proposed as the GPP-based SR platform, for example, multicore Central Processing Unit (CPU), Graphic Processing Unit (GPU) and Cell processors. In this paper, the Cell processor is considered as the core component in the GPP-based SR platform, and the channel decoding modules for convolutional, Turbo and Low-density parity-check (LDPC) codes of WiMAX systems are investigated and efficiently implemented on Cell processor. With a single Synergistic Processor Element (SPE) running at 3.2GHz, the implemented channel decoders can throughput up to 30Mbps, 1.36Mbps and 1.71Mbps for the above three codes, respectively. Moreover, the decoding modules can be easily integrated to the SR system and can provide a highly integrated SR solution.","PeriodicalId":37804,"journal":{"name":"Majlesi Journal of Electrical Engineering","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"High Performance Channel Decoders on CELL Broadband Engine for WiMAX System\",\"authors\":\"Chen Xiang, Zhao Ming, Zhao Juntao, C. Jianwen, Wang Jing\",\"doi\":\"10.1234/MJEE.V5I1.377\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Wireless baseband processing, which is characterized by high computational complexity and high data throughput, is regarded as the most challenging issue for software radio (SR) systems, especially for the General Purpose Processor (GPP)-based SR systems. To overcome this implementation difficulty in SR systems, the multicore architecture has been proposed as the GPP-based SR platform, for example, multicore Central Processing Unit (CPU), Graphic Processing Unit (GPU) and Cell processors. In this paper, the Cell processor is considered as the core component in the GPP-based SR platform, and the channel decoding modules for convolutional, Turbo and Low-density parity-check (LDPC) codes of WiMAX systems are investigated and efficiently implemented on Cell processor. With a single Synergistic Processor Element (SPE) running at 3.2GHz, the implemented channel decoders can throughput up to 30Mbps, 1.36Mbps and 1.71Mbps for the above three codes, respectively. Moreover, the decoding modules can be easily integrated to the SR system and can provide a highly integrated SR solution.\",\"PeriodicalId\":37804,\"journal\":{\"name\":\"Majlesi Journal of Electrical Engineering\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-01-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Majlesi Journal of Electrical Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1234/MJEE.V5I1.377\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"Engineering\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Majlesi Journal of Electrical Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1234/MJEE.V5I1.377","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"Engineering","Score":null,"Total":0}
High Performance Channel Decoders on CELL Broadband Engine for WiMAX System
Wireless baseband processing, which is characterized by high computational complexity and high data throughput, is regarded as the most challenging issue for software radio (SR) systems, especially for the General Purpose Processor (GPP)-based SR systems. To overcome this implementation difficulty in SR systems, the multicore architecture has been proposed as the GPP-based SR platform, for example, multicore Central Processing Unit (CPU), Graphic Processing Unit (GPU) and Cell processors. In this paper, the Cell processor is considered as the core component in the GPP-based SR platform, and the channel decoding modules for convolutional, Turbo and Low-density parity-check (LDPC) codes of WiMAX systems are investigated and efficiently implemented on Cell processor. With a single Synergistic Processor Element (SPE) running at 3.2GHz, the implemented channel decoders can throughput up to 30Mbps, 1.36Mbps and 1.71Mbps for the above three codes, respectively. Moreover, the decoding modules can be easily integrated to the SR system and can provide a highly integrated SR solution.
期刊介绍：
The scope of Majlesi Journal of Electrcial Engineering (MJEE) is ranging from mathematical foundation to practical engineering design in all areas of electrical engineering. The editorial board is international and original unpublished papers are welcome from throughout the world. The journal is devoted primarily to research papers, but very high quality survey and tutorial papers are also published. There is no publication charge for the authors.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
