{"title":"基于LFSR的边界函数宽边测试生成","authors":"Irith Pomeranz","doi":"10.1049/iet-cdt.2019.0058","DOIUrl":null,"url":null,"abstract":"<div>\n <p>This study considers the compression of a type of close-to-functional broadside tests called boundary-functional broadside tests when the on-chip decompression logic consists of a linear-feedback shift register (LFSR). Boundary-functional broadside tests maintain functional operation conditions on a set of lines (called a boundary) in a circuit. This limits the deviations from functional operation conditions by ensuring that they do not propagate across the boundary. Functional vectors for the boundary are obtained from functional broadside tests. Seeds for the LFSR are generated directly from functional boundary vectors without generating tests or test cubes. Considering the tests that the LFSR produces, the seed generation procedure attempts to obtain the lowest possible Hamming distance between their boundary vectors and functional boundary vectors. It considers multiple LFSRs with increasing lengths to achieve test data compression. The procedure is structured to explore the trade-off between the level of test data compression and the Hamming distances or the proximity to functional operation conditions.</p>\n </div>","PeriodicalId":50383,"journal":{"name":"IET Computers and Digital Techniques","volume":"14 2","pages":"61-68"},"PeriodicalIF":1.1000,"publicationDate":"2019-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1049/iet-cdt.2019.0058","citationCount":"1","resultStr":"{\"title\":\"LFSR-based generation of boundary-functional broadside tests\",\"authors\":\"Irith Pomeranz\",\"doi\":\"10.1049/iet-cdt.2019.0058\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div>\\n <p>This study considers the compression of a type of close-to-functional broadside tests called boundary-functional broadside tests when the on-chip decompression logic consists of a linear-feedback shift register (LFSR). Boundary-functional broadside tests maintain functional operation conditions on a set of lines (called a boundary) in a circuit. This limits the deviations from functional operation conditions by ensuring that they do not propagate across the boundary. Functional vectors for the boundary are obtained from functional broadside tests. Seeds for the LFSR are generated directly from functional boundary vectors without generating tests or test cubes. Considering the tests that the LFSR produces, the seed generation procedure attempts to obtain the lowest possible Hamming distance between their boundary vectors and functional boundary vectors. It considers multiple LFSRs with increasing lengths to achieve test data compression. The procedure is structured to explore the trade-off between the level of test data compression and the Hamming distances or the proximity to functional operation conditions.</p>\\n </div>\",\"PeriodicalId\":50383,\"journal\":{\"name\":\"IET Computers and Digital Techniques\",\"volume\":\"14 2\",\"pages\":\"61-68\"},\"PeriodicalIF\":1.1000,\"publicationDate\":\"2019-09-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1049/iet-cdt.2019.0058\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IET Computers and Digital Techniques\",\"FirstCategoryId\":\"94\",\"ListUrlMain\":\"https://onlinelibrary.wiley.com/doi/10.1049/iet-cdt.2019.0058\",\"RegionNum\":4,\"RegionCategory\":\"计算机科学\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Computers and Digital Techniques","FirstCategoryId":"94","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1049/iet-cdt.2019.0058","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
LFSR-based generation of boundary-functional broadside tests
This study considers the compression of a type of close-to-functional broadside tests called boundary-functional broadside tests when the on-chip decompression logic consists of a linear-feedback shift register (LFSR). Boundary-functional broadside tests maintain functional operation conditions on a set of lines (called a boundary) in a circuit. This limits the deviations from functional operation conditions by ensuring that they do not propagate across the boundary. Functional vectors for the boundary are obtained from functional broadside tests. Seeds for the LFSR are generated directly from functional boundary vectors without generating tests or test cubes. Considering the tests that the LFSR produces, the seed generation procedure attempts to obtain the lowest possible Hamming distance between their boundary vectors and functional boundary vectors. It considers multiple LFSRs with increasing lengths to achieve test data compression. The procedure is structured to explore the trade-off between the level of test data compression and the Hamming distances or the proximity to functional operation conditions.
期刊介绍:
IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.
The key subject areas of interest are:
Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.
Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.
Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.
Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.
Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.
Case Studies: emerging applications, applications in industrial designs, and design frameworks.