HLL enhancement for stack based processors

Stack machines, or stack based processors, have long been pigeon-holed as FORTH processors; specialised devices with little relevance for high level language applications. The failure of stack machines to address the issue of high level language support, and C in particular, has prevented wider acceptance of this promising technology despite the potential benefits of simpler hardware and low gate counts. Our research has centred upon eliminating cache and memory dependence, reducing the limits imposed by external bandwidths^◊. Having previously introduced a compact multiple-instruction-per-word stack-based encoding strategy in [Bailey93a], we now present a revised model, assessing its performance with compiled C benchmarks^⧫, and stressing minimisation of memory dependence.