T. Ahn, G. Chen, B. Hua, C.J. Kim, D. Knee, A. Kondo, B. Kuo, I.J. Lan, M. Ng, F. Shen, N.H. Yeh, J.K. Young
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A PRML (Partial Response Maximum Likelihood) channel chip employing a mixed-signal 0.8 /spl mu/m BiCMOS process for hard disk drive (HDD) applications is described. This chip performs the complete write, read, and servo functions using only five external components with a data rate of up to 120 Mb/sec. Under normal operating conditions the power dissipation is less than 800 mW. The on-chip circuitry includes ADC, VGA, FIR filter, Viterbi decoder, two PLL's, etc.
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