{"title":"采用自举技术的0.8 V CMOS TSPC绝热DCVS逻辑电路，用于低功耗VLSI","authors":"Hung-Pin Chen, J. Kuo","doi":"10.1109/ICECS.2004.1399643","DOIUrl":null,"url":null,"abstract":"The paper reports a novel 0.8 V CMOS true-single-phase-clocking (TSPC) adiabatic differential cascode voltage switch (DCVS) logic circuit with the bootstrap technique for low-power VLSI. Via the pass transistors and compensating transistors, the TSPC scheme has been obtained for easy clocking. Using the capacitance coupling from the bootstrap transistors, this 0.8 V TSPC adiabatic DCVS logic circuit with the bootstrap technique consumes 31% less energy as compared to the one using the clocked adiabatic latch (CAL) approach.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI\",\"authors\":\"Hung-Pin Chen, J. Kuo\",\"doi\":\"10.1109/ICECS.2004.1399643\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper reports a novel 0.8 V CMOS true-single-phase-clocking (TSPC) adiabatic differential cascode voltage switch (DCVS) logic circuit with the bootstrap technique for low-power VLSI. Via the pass transistors and compensating transistors, the TSPC scheme has been obtained for easy clocking. Using the capacitance coupling from the bootstrap transistors, this 0.8 V TSPC adiabatic DCVS logic circuit with the bootstrap technique consumes 31% less energy as compared to the one using the clocked adiabatic latch (CAL) approach.\",\"PeriodicalId\":38467,\"journal\":{\"name\":\"Giornale di Storia Costituzionale\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Giornale di Storia Costituzionale\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2004.1399643\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"Arts and Humanities\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Giornale di Storia Costituzionale","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2004.1399643","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"Arts and Humanities","Score":null,"Total":0}
引用次数: 10
摘要
本文报道了一种新颖的0.8 V CMOS真单相时钟(TSPC)绝热差分级联电压开关(DCVS)逻辑电路，该电路采用自举技术用于低功耗VLSI。通过通通晶体管和补偿晶体管，获得了易于实现时钟的TSPC方案。利用自举晶体管的电容耦合，这种采用自举技术的0.8 V TSPC绝热DCVS逻辑电路比采用时钟绝热锁存器(CAL)方法的电路能耗低31%。
A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI
The paper reports a novel 0.8 V CMOS true-single-phase-clocking (TSPC) adiabatic differential cascode voltage switch (DCVS) logic circuit with the bootstrap technique for low-power VLSI. Via the pass transistors and compensating transistors, the TSPC scheme has been obtained for easy clocking. Using the capacitance coupling from the bootstrap transistors, this 0.8 V TSPC adiabatic DCVS logic circuit with the bootstrap technique consumes 31% less energy as compared to the one using the clocked adiabatic latch (CAL) approach.
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