{"title":"利用VLSI技术设计更快、更节能的感测放大器","authors":"A. Pathrikar, R. Deshpande","doi":"10.1109/ICAECCT.2016.7942613","DOIUrl":null,"url":null,"abstract":"In this paper we have designed Faster & Power Efficient Sense Amplifier for CMOS SRAM using VLSI Technology i.e. primarily schematic of sense amplifier is designed & simulated using ADS (Advanced Design System). The sense amplifier then implemented & analyzed at chip level using Microwind 3.1- a layout editor. The 45 nm & 32 nm technologies are used to analyze performance of Sense Amplifier. Our focus will be to reduce the size, to improve the power consumption and also to improve the response time of sense amplifier.","PeriodicalId":6629,"journal":{"name":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","volume":"173 1","pages":"358-361"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Design of faster & power efficient sense amplifier using VLSI technology\",\"authors\":\"A. Pathrikar, R. Deshpande\",\"doi\":\"10.1109/ICAECCT.2016.7942613\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we have designed Faster & Power Efficient Sense Amplifier for CMOS SRAM using VLSI Technology i.e. primarily schematic of sense amplifier is designed & simulated using ADS (Advanced Design System). The sense amplifier then implemented & analyzed at chip level using Microwind 3.1- a layout editor. The 45 nm & 32 nm technologies are used to analyze performance of Sense Amplifier. Our focus will be to reduce the size, to improve the power consumption and also to improve the response time of sense amplifier.\",\"PeriodicalId\":6629,\"journal\":{\"name\":\"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)\",\"volume\":\"173 1\",\"pages\":\"358-361\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICAECCT.2016.7942613\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Conference on Advances in Electronics, Communication and Computer Technology (ICAECCT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICAECCT.2016.7942613","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of faster & power efficient sense amplifier using VLSI technology
In this paper we have designed Faster & Power Efficient Sense Amplifier for CMOS SRAM using VLSI Technology i.e. primarily schematic of sense amplifier is designed & simulated using ADS (Advanced Design System). The sense amplifier then implemented & analyzed at chip level using Microwind 3.1- a layout editor. The 45 nm & 32 nm technologies are used to analyze performance of Sense Amplifier. Our focus will be to reduce the size, to improve the power consumption and also to improve the response time of sense amplifier.
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