Kenichi Maruko, Tatsuya Sugioka, H. Hayashi, Zhiwei Zhou, Yasunori Tsukuda, Y. Yagishita, H. Konishi, Toshikyuki Ogata, Hisashi Owa, T. Niki, K. Konda, M. Sato, Hiroshi Shiroshita, Takeshi Ogura, T. Aoki, H. Kihara, Sachiya Tanaka
{"title":"基于双边缘注入锁定振荡器的1.296 ~ 5.184Gb/s突发模式CDR收发器","authors":"Kenichi Maruko, Tatsuya Sugioka, H. Hayashi, Zhiwei Zhou, Yasunori Tsukuda, Y. Yagishita, H. Konishi, Toshikyuki Ogata, Hisashi Owa, T. Niki, K. Konda, M. Sato, Hiroshi Shiroshita, Takeshi Ogura, T. Aoki, H. Kihara, Sachiya Tanaka","doi":"10.1109/ISSCC.2010.5433821","DOIUrl":null,"url":null,"abstract":"Since the I/O bandwidth demand for mobile consumer electronics has been growing rapidly, the importance of high-speed low-power I/O links has also been increasing. Among proposed I/O architectures, [1] and [2] are attractive solutions. However, for an application that needs the burst-mode operation, the lock-in time should be within the period of several tens of bits. Therefore, the PLL-based phase rotator with a longer lock-in time, is not suitable for this purpose. In this paper, a 1.296-to-5.184Gb/s transceiver uses an injection-locking-based CDR. The proposed CDR architecture, dual-edge injection-locked oscillator CDR (DILO-CDR), realizes fast lock (≪20 bits), continuous-rate capability (1.296 to 5.184Gb/s) and 2× power efficiency [2.4mW/(Gb/s)] of previous fast-lock continuous-rate CDRs [3, 4].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"170 1","pages":"364-365"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":"{\"title\":\"A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator\",\"authors\":\"Kenichi Maruko, Tatsuya Sugioka, H. Hayashi, Zhiwei Zhou, Yasunori Tsukuda, Y. Yagishita, H. Konishi, Toshikyuki Ogata, Hisashi Owa, T. Niki, K. Konda, M. Sato, Hiroshi Shiroshita, Takeshi Ogura, T. Aoki, H. Kihara, Sachiya Tanaka\",\"doi\":\"10.1109/ISSCC.2010.5433821\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Since the I/O bandwidth demand for mobile consumer electronics has been growing rapidly, the importance of high-speed low-power I/O links has also been increasing. Among proposed I/O architectures, [1] and [2] are attractive solutions. However, for an application that needs the burst-mode operation, the lock-in time should be within the period of several tens of bits. Therefore, the PLL-based phase rotator with a longer lock-in time, is not suitable for this purpose. In this paper, a 1.296-to-5.184Gb/s transceiver uses an injection-locking-based CDR. The proposed CDR architecture, dual-edge injection-locked oscillator CDR (DILO-CDR), realizes fast lock (≪20 bits), continuous-rate capability (1.296 to 5.184Gb/s) and 2× power efficiency [2.4mW/(Gb/s)] of previous fast-lock continuous-rate CDRs [3, 4].\",\"PeriodicalId\":6418,\"journal\":{\"name\":\"2010 IEEE International Solid-State Circuits Conference - (ISSCC)\",\"volume\":\"170 1\",\"pages\":\"364-365\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"34\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Solid-State Circuits Conference - (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2010.5433821\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2010.5433821","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator
Since the I/O bandwidth demand for mobile consumer electronics has been growing rapidly, the importance of high-speed low-power I/O links has also been increasing. Among proposed I/O architectures, [1] and [2] are attractive solutions. However, for an application that needs the burst-mode operation, the lock-in time should be within the period of several tens of bits. Therefore, the PLL-based phase rotator with a longer lock-in time, is not suitable for this purpose. In this paper, a 1.296-to-5.184Gb/s transceiver uses an injection-locking-based CDR. The proposed CDR architecture, dual-edge injection-locked oscillator CDR (DILO-CDR), realizes fast lock (≪20 bits), continuous-rate capability (1.296 to 5.184Gb/s) and 2× power efficiency [2.4mW/(Gb/s)] of previous fast-lock continuous-rate CDRs [3, 4].