三维电网建模

Q3 Arts and Humanities Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI:10.1109/ICECS.2004.1399631

Larissa Zlydina, Y. Yagil

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引用次数: 6

摘要

本文描述了用于高性能CPU设计的片上三维电网(PG)建模。我们表明，对于高频(1 GHz以上)，有必要使用提取部分自导体和互导体电感的全RLM PG模型，而不是电阻R或RL模型。我们还提出了一种实用的模型缩减技术，称为“真实空间缩减”(RSR)，它可以简化模型，减少内存和仿真时间，而不会造成显著的精度损失。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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3D power grid modeling

The paper describes on-chip 3D power grid (PG) modeling for high performance CPU designs. We show that for high frequencies (above 1 GHz) it is necessary to use the full RLM PG model with extracted partial self and mutual conductors' inductances, rather than resistive R or RL models. We also present a practical model reduction technique named "real space reduction" (RSR), which enables simplifying the model and reduces memory and simulation time without significant accuracy losses.

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