A sub-1.55mV-accuracy 36.9ps-FOM digital-low-dropout regulator employing switched-capacitor resistance

Modern DVFS-enabled SoCs require nimble supply regulators that rapidly respond to abrupt load changes and offer fine resolution (e.g., 12.5mV in [1], 10mV in [2]) over large voltage and current dynamic ranges. Switch-array digital LDOs (SA-DLDOs) are a potentially attractive regulation option due to their ability to operate with low input voltages and in part to their modular digital nature and scalability. SA-DLDOs employ 2” unary-[3] or binary-weighted [4] PMOS arrays that are modulated through a 1b or multi-bit ADCs to maintain the output voltage (Vout) at the desired level (Vref), as shown in Fig. 18.7.1 (top left). Unfortunately, while array conductance in SA-DLDOs linearly increases with equal step size (gLSB) as the code is increased, the output voltage step, vLSB, does not; in fact, vLsB is nonlinear: ∼GLVout × GLSB. Thus, SA-DLDOs achieve a nonlinear steady-state error, ess = Veef − Vout ≈ ±gLSB/Gl χ Vú!op, as shown in Fig. 18.7.1 (bottom left), that deteriorates at large dropout voltages, Vdrop = Vin − Voitt, and at small loads, Gl. As a result, the required supply step of 10mV (with ±15% typical accuracy) to perform per-core DVFS over a typical 100χ IL dynamic range requires an impractical 16b PMOS array resolution. Even with limit-cycle oscillations, the load range that can achieve ±1.5mV accuracy is provably limited to 2^{N-6, 7} at Veef=VJ2 (Fig. 18.7.2, top left), which would still require a 14b array resolution that, even if it were feasible to build, would come with linearly (for binary search) or exponentially (for linear search) increased response time (TR), quiescent power (IQ), and area.