存储器中硅蚀刻工艺的研究

2017 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2017-03-01 DOI:10.1109/CSTIC.2017.7919779

Rong-Yao Chang, Yi-ying Zhang, Hai-yang Zhang

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引用次数: 1

摘要

随着模式CD(临界尺寸)的缩小，模式坍塌、微加载效应和硅对二氧化硅的选择性在STI(浅沟隔离)模式中变得更加具有挑战性。图案坍塌与微加载效应密切相关。为了提高Si对SiO2的选择性和抑制微加载效应，采用了偏置射频脉冲和周期蚀刻[1]。本文讨论了空间CD差对硅蚀刻过程中微加载效应和偏置射频脉冲函数的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A study of silicon etch process in memory process

With the shrinkage of pattern CD (Critical Dimension), pattern collapse, micro-loading effect and silicon to silicon dioxide selectivity become more challenging in STI (Shallow Trench Isolation) patterning. Pattern collapse is closely related to micro-loading effect. To enhance Si to SiO2 selectivity and suppress micro-loading effect, bias RF pulsing and cycle etch are used [1]. In this paper, the influence of space CD difference on micro-loading effect and bias RF pulsing function in silicon etch process is discussed.

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2017 China Semiconductor Technology International Conference (CSTIC)

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