小值集成自感器设计准则

Q3 Arts and Humanities Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI:10.1109/ICECS.2004.1399725
G. Petit, R. Kielbasa, V. Petit
{"title":"小值集成自感器设计准则","authors":"G. Petit, R. Kielbasa, V. Petit","doi":"10.1109/ICECS.2004.1399725","DOIUrl":null,"url":null,"abstract":"Facing the increased frequencies used in analog products, integrated-circuit designers find that the X or upper band has its own problems, especially in the case of passive components. The paper focuses on inductor design and layout, opposing classical analog integrated inductors and hyper frequency lines. After studying separately each solution and pointing out their limits on an actual SOS (silicon on sapphire) 0.5 /spl mu/m case, a methodology to solve this issue is revealed and a chosen criterion is supplied.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"68 1","pages":"491-494"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Criterion of design for small value integrated self-inductors\",\"authors\":\"G. Petit, R. Kielbasa, V. Petit\",\"doi\":\"10.1109/ICECS.2004.1399725\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Facing the increased frequencies used in analog products, integrated-circuit designers find that the X or upper band has its own problems, especially in the case of passive components. The paper focuses on inductor design and layout, opposing classical analog integrated inductors and hyper frequency lines. After studying separately each solution and pointing out their limits on an actual SOS (silicon on sapphire) 0.5 /spl mu/m case, a methodology to solve this issue is revealed and a chosen criterion is supplied.\",\"PeriodicalId\":38467,\"journal\":{\"name\":\"Giornale di Storia Costituzionale\",\"volume\":\"68 1\",\"pages\":\"491-494\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Giornale di Storia Costituzionale\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2004.1399725\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"Arts and Humanities\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Giornale di Storia Costituzionale","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2004.1399725","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"Arts and Humanities","Score":null,"Total":0}
引用次数: 2

摘要

面对模拟产品中使用频率的增加,集成电路设计人员发现X或上频段有其自身的问题,特别是在无源元件的情况下。针对传统的模拟集成电感和超频线路,本文重点研究了电感的设计和布局。在分别研究了每种解决方案并指出其在实际SOS(蓝宝石上硅)0.5 /spl mu/m情况下的限制后,揭示了解决该问题的方法并提供了选择的标准。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Criterion of design for small value integrated self-inductors
Facing the increased frequencies used in analog products, integrated-circuit designers find that the X or upper band has its own problems, especially in the case of passive components. The paper focuses on inductor design and layout, opposing classical analog integrated inductors and hyper frequency lines. After studying separately each solution and pointing out their limits on an actual SOS (silicon on sapphire) 0.5 /spl mu/m case, a methodology to solve this issue is revealed and a chosen criterion is supplied.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
Giornale di Storia Costituzionale
Giornale di Storia Costituzionale Arts and Humanities-History
CiteScore
0.20
自引率
0.00%
发文量
0
期刊最新文献
PD diagnosis on medium voltage cables with oscillating voltage (OWTS) Spintronic logic circuit design for nanoscale computation A 0.8 V CMOS TSPC adiabatic DCVS logic circuit with the bootstrap technique for low-power VLSI Efficient Gabor expansion using non minimal dual Gabor windows 3D power grid modeling
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1