{"title":"基于GPU的软件DVB-T接收机设计","authors":"K. Lee, S. Heo","doi":"10.1109/ICCE.2013.6487027","DOIUrl":null,"url":null,"abstract":"This paper presents the GPU based software DVB-T receiver design. We first propose the software DVB-T receiver using just one CPU core and investigate the gap between the required time budget and the actual simulation time. Based on the simulation results we partition the algorithm such that some of the algorithm corresponding to the critical path can be processed by the GPU which adopts massively parallel processing elements. To increase the thread usage we design software algorithms which reduce the FFT and Viterbi decoding processing time by the ratio of 10~20 times compared with the CPU based processing.","PeriodicalId":6432,"journal":{"name":"2013 IEEE International Conference on Consumer Electronics (ICCE)","volume":"16 1","pages":"582-585"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"GPU based software DVB-T receiver design\",\"authors\":\"K. Lee, S. Heo\",\"doi\":\"10.1109/ICCE.2013.6487027\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the GPU based software DVB-T receiver design. We first propose the software DVB-T receiver using just one CPU core and investigate the gap between the required time budget and the actual simulation time. Based on the simulation results we partition the algorithm such that some of the algorithm corresponding to the critical path can be processed by the GPU which adopts massively parallel processing elements. To increase the thread usage we design software algorithms which reduce the FFT and Viterbi decoding processing time by the ratio of 10~20 times compared with the CPU based processing.\",\"PeriodicalId\":6432,\"journal\":{\"name\":\"2013 IEEE International Conference on Consumer Electronics (ICCE)\",\"volume\":\"16 1\",\"pages\":\"582-585\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-03-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Conference on Consumer Electronics (ICCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE.2013.6487027\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference on Consumer Electronics (ICCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.2013.6487027","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents the GPU based software DVB-T receiver design. We first propose the software DVB-T receiver using just one CPU core and investigate the gap between the required time budget and the actual simulation time. Based on the simulation results we partition the algorithm such that some of the algorithm corresponding to the critical path can be processed by the GPU which adopts massively parallel processing elements. To increase the thread usage we design software algorithms which reduce the FFT and Viterbi decoding processing time by the ratio of 10~20 times compared with the CPU based processing.
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