VLSI implementation of the universal 2-D CAT/ICAT system

The VLSI implementation of the universal two-dimensional (2D) cellular automata transform (CAT) as well as inverse CAT (ICAT) is present in this paper. The universal 2D CAT/ICAT chip is based on the 2D CAB generator. To facilitate the development of a universal 2D CAB generator, we adopted a CA cell structure with programmable additive rules to generate 1D CAB first, and then utilized the canonical products of 2D CAB to perform the 2D CAB. We have accomplished simulations of the universal 2D 8/spl times/8 CAT/ICAT chip by using CANDENCE tools. We also have completed the circuit synthesis of the 2D CAT/ICAT chip by using the SYNOPSE tools with the TSMC 0.35 /spl mu/m CMOS data-path cell-library. The maximum operation frequency was 120 MHz, and the area size was 6.8225 mm/sup 2/. It shows that the architecture of the proposed universal 2D CAT/ICAT is suitable for VLSI realization.