{"title":"新型相位误差小的分数n锁相环频率合成器","authors":"Y. Sumi, S. Obote, K. Tsuda, K. Syoubu, Y. Fukui","doi":"10.1109/APCAS.1996.569215","DOIUrl":null,"url":null,"abstract":"Conventionally, the division ratio of the programmable divider in the Phase Locked Loop (PLL) frequency synthesizer is an only integer. Therefore, it has been hoped to realize the fractional-N programmable divider which can divide not only an integer step but also a fractional step. In this paper, a new fractional-N programmable divider for the PLL frequency synthesizer is proposed. In this divider, the width of phase error pulse which phase detector produces in every period of reference frequency is decreased by introducing the new division ratio (N+1/2) besides N and (N+1).","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Novel fractional-N PLL frequency synthesizer with reduced phase error\",\"authors\":\"Y. Sumi, S. Obote, K. Tsuda, K. Syoubu, Y. Fukui\",\"doi\":\"10.1109/APCAS.1996.569215\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Conventionally, the division ratio of the programmable divider in the Phase Locked Loop (PLL) frequency synthesizer is an only integer. Therefore, it has been hoped to realize the fractional-N programmable divider which can divide not only an integer step but also a fractional step. In this paper, a new fractional-N programmable divider for the PLL frequency synthesizer is proposed. In this divider, the width of phase error pulse which phase detector produces in every period of reference frequency is decreased by introducing the new division ratio (N+1/2) besides N and (N+1).\",\"PeriodicalId\":20507,\"journal\":{\"name\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCAS.1996.569215\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCAS.1996.569215","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Novel fractional-N PLL frequency synthesizer with reduced phase error
Conventionally, the division ratio of the programmable divider in the Phase Locked Loop (PLL) frequency synthesizer is an only integer. Therefore, it has been hoped to realize the fractional-N programmable divider which can divide not only an integer step but also a fractional step. In this paper, a new fractional-N programmable divider for the PLL frequency synthesizer is proposed. In this divider, the width of phase error pulse which phase detector produces in every period of reference frequency is decreased by introducing the new division ratio (N+1/2) besides N and (N+1).