P. Diodato, J. O'Neill, Y. Wong, G. Alers, H. Vaidya, S. Chaudhry, W. S. Lindenberger, A. C. Dumbri, C. Liu, W. Lai
{"title":"嵌入式DRAM:一个元件和电路的评估","authors":"P. Diodato, J. O'Neill, Y. Wong, G. Alers, H. Vaidya, S. Chaudhry, W. S. Lindenberger, A. C. Dumbri, C. Liu, W. Lai","doi":"10.1109/CICC.2000.852669","DOIUrl":null,"url":null,"abstract":"Embedded DRAM memory cells employing advanced capacitor dielectrics (Ta/sub 2/O/sub 5/) have been designed, fabricated, and measured. Memory cell data retention time is used to compare capacitor characteristics between four Ta/sub 2/O/sub 5/ equipment vendors. Static behavior in one type of DRAM cell is attributed to the bimodal current-voltage characteristic of the Ta/sub 2/O/sub 5/, and circuit topography.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"53 1","pages":"291-294"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Embedded DRAM: an element and circuit evaluation\",\"authors\":\"P. Diodato, J. O'Neill, Y. Wong, G. Alers, H. Vaidya, S. Chaudhry, W. S. Lindenberger, A. C. Dumbri, C. Liu, W. Lai\",\"doi\":\"10.1109/CICC.2000.852669\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Embedded DRAM memory cells employing advanced capacitor dielectrics (Ta/sub 2/O/sub 5/) have been designed, fabricated, and measured. Memory cell data retention time is used to compare capacitor characteristics between four Ta/sub 2/O/sub 5/ equipment vendors. Static behavior in one type of DRAM cell is attributed to the bimodal current-voltage characteristic of the Ta/sub 2/O/sub 5/, and circuit topography.\",\"PeriodicalId\":20702,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"volume\":\"53 1\",\"pages\":\"291-294\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2000.852669\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852669","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Embedded DRAM memory cells employing advanced capacitor dielectrics (Ta/sub 2/O/sub 5/) have been designed, fabricated, and measured. Memory cell data retention time is used to compare capacitor characteristics between four Ta/sub 2/O/sub 5/ equipment vendors. Static behavior in one type of DRAM cell is attributed to the bimodal current-voltage characteristic of the Ta/sub 2/O/sub 5/, and circuit topography.
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