TLP:迈向三层循环并行化

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IET Computers and Digital Techniques Pub Date : 2022-08-09 DOI:10.1049/cdt2.12046
Shabnam Mahjoub, Mehdi Golsorkhtabaramiri, Seyed Sadegh Salehi Amiri
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引用次数: 1

摘要

由于计算机系统是以多核和/或多处理器形式设计的,因此可以使用处理器的最大容量来通过并行化以最少的时间消耗运行应用程序。这是并行编译器的责任,它通过在不同的处理器之间分配迭代并同时执行它们来分几个步骤执行并行化,以实现更低的运行时间。本文将三层完美嵌套循环的均匀化作为并行化的重要步骤,并提出了一种称为“迈向三层循环并行化”(TLP)的方法,该方法使用青蛙跳跃算法和模糊算法的组合来实现最佳结果,因为近年来,许多算法都用于体积数据,即三维空间。与现有方法相比,TLP算法的实现结果在所需时间内产生了各种各样的最优结果,并且由向量产生的锥尺寸最小。并对输入依赖向量的最大数量进行了分解。这些结果可以加速生成并行代码的过程,并促进其用于高性能计算目的的开发。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

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TLP: Towards three-level loop parallelisation

Due to the design of computer systems in the multi-core and/or multi-processor form, it is possible to use the maximum capacity of processors to run an application with the least time consumed through parallelisation. This is the responsibility of parallel compilers, which perform parallelisation in several steps by distributing iterations between different processors and executing them simultaneously to achieve lower runtime. The present paper focuses on the uniformisation of three-level perfect nested loops as an important step in parallelisation and proposes a method called Towards Three-Level Loop Parallelisation (TLP) that uses a combination of a Frog Leaping Algorithm and Fuzzy to achieve optimal results because in recent years, many algorithms have worked on volumetric data, that is, three-dimensional spaces. Results of the implementation of the TLP algorithm in comparison with existing methods lead to a wide variety of optimal results at desired times, with minimum cone size resulting from the vectors. Besides, the maximum number of input dependence vectors is decomposed by this algorithm. These results can accelerate the process of generating parallel codes and facilitate their development for High-Performance Computing purposes.

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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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