Combined ac and Transient Power Distribution Analysis

The increased use of noise sensitive circuits and power up or sleep modes, and the high cost of on-chip decoupling have combined to make the VLSI CMOS power distribution problem both a global chip and a local circuit concern. Extensive simulation is required to evaluate the worst case power rail sag due to the enormous possibilities in power up sequences. Moreovel; VLJI CMOS power distribution networks are nonideal in that they fail to provide a low impedance path from the power supply all the way to the circuit terminals over a large range ojjcrequencies [2,3]. Resonant peaks typically litter the impedmce spectrum, even at the chip level [IO], making both transient and steady state analysis necessary. This paper proposes an analysis formulation that eficiently derives both steady state and transient responses from a series of fixed-time point transient impulse response solutions (frequency-shifted moments). This formulation is used to eficiently evaluate worst case power supply sags. Practical examples holving VLSI CMOS power distribution networks are shown which demonstrate that phase-shifts across the chip further complicate the calculation of the worst case voltage sag.