{"title":"锁相和锁延迟系统的非线性行为建模与仿真","authors":"Lin Wu, Huawen Jin, W. Black","doi":"10.1109/CICC.2000.852705","DOIUrl":null,"url":null,"abstract":"This paper presents a new method for modeling VCO and Voltage Controlled Delay Line (VCDL) circuits that allows inclusion of device noise and supply coupling effects with simplified numerical computation. PLL and DLL behavioral simulations allow accurate prediction of system performance during both locked and unlocked conditions with a great reduction in CPU time over transistor level simulators. Simulation results are presented and compared with theoretical predictions and measurement results, that demonstrate the effectiveness of this scheme.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"120 1","pages":"447-450"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systems\",\"authors\":\"Lin Wu, Huawen Jin, W. Black\",\"doi\":\"10.1109/CICC.2000.852705\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new method for modeling VCO and Voltage Controlled Delay Line (VCDL) circuits that allows inclusion of device noise and supply coupling effects with simplified numerical computation. PLL and DLL behavioral simulations allow accurate prediction of system performance during both locked and unlocked conditions with a great reduction in CPU time over transistor level simulators. Simulation results are presented and compared with theoretical predictions and measurement results, that demonstrate the effectiveness of this scheme.\",\"PeriodicalId\":20702,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"volume\":\"120 1\",\"pages\":\"447-450\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2000.852705\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852705","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Nonlinear behavioral modeling and simulation of phase-locked and delay-locked systems
This paper presents a new method for modeling VCO and Voltage Controlled Delay Line (VCDL) circuits that allows inclusion of device noise and supply coupling effects with simplified numerical computation. PLL and DLL behavioral simulations allow accurate prediction of system performance during both locked and unlocked conditions with a great reduction in CPU time over transistor level simulators. Simulation results are presented and compared with theoretical predictions and measurement results, that demonstrate the effectiveness of this scheme.
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