{"title":"基于集群的内存fpga结构","authors":"Jason P. Clifford, S. Wilton","doi":"10.1109/CICC.2000.852633","DOIUrl":null,"url":null,"abstract":"Embedded memory has become an essential part of FPGAs. In this paper, we investigate how a particular FPGA architecture can be enhanced by including a single memory array in each logic cluster. It is shown that the best overall speed and density results when a cluster contains between 16 and 20 logic elements and one memory array with 512 or 1024 bits. It is also shown that 40% of the logic and memory element inputs should be available outside the cluster.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"17 1","pages":"131-134"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Architecture of cluster-based FPGAs with memory\",\"authors\":\"Jason P. Clifford, S. Wilton\",\"doi\":\"10.1109/CICC.2000.852633\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Embedded memory has become an essential part of FPGAs. In this paper, we investigate how a particular FPGA architecture can be enhanced by including a single memory array in each logic cluster. It is shown that the best overall speed and density results when a cluster contains between 16 and 20 logic elements and one memory array with 512 or 1024 bits. It is also shown that 40% of the logic and memory element inputs should be available outside the cluster.\",\"PeriodicalId\":20702,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"volume\":\"17 1\",\"pages\":\"131-134\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2000.852633\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852633","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Embedded memory has become an essential part of FPGAs. In this paper, we investigate how a particular FPGA architecture can be enhanced by including a single memory array in each logic cluster. It is shown that the best overall speed and density results when a cluster contains between 16 and 20 logic elements and one memory array with 512 or 1024 bits. It is also shown that 40% of the logic and memory element inputs should be available outside the cluster.
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