{"title":"一种适用于SoC的高增益片上天线的设计","authors":"Yexi Song, Yunqiu Wu, Jie Yang, K. Kang","doi":"10.1109/IMWS-AMP.2015.7324967","DOIUrl":null,"url":null,"abstract":"A V-band high gain and high efficiency on-chip antenna in a CMOS 0.18-μm process is presented in this work. High resistivity silicon substrate, dielectric resonator and a layer of off-chip ground are used in this design to enhance the antenna gain and reduce the antenna size. The proposed antenna achieves a maximum gain of 8 dBi with a -10 dB bandwidth of 4 GHz. The peak antenna efficiency is 96.7% and the half-power-beamwidth is 72° and 92° in the E-and H-plane respectively. Moreover, the chip size of the presented antenna is 700 μm × 1250 μm.","PeriodicalId":6625,"journal":{"name":"2015 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP)","volume":"131 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2015-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"The design of a high gain on-chip antenna for SoC application\",\"authors\":\"Yexi Song, Yunqiu Wu, Jie Yang, K. Kang\",\"doi\":\"10.1109/IMWS-AMP.2015.7324967\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A V-band high gain and high efficiency on-chip antenna in a CMOS 0.18-μm process is presented in this work. High resistivity silicon substrate, dielectric resonator and a layer of off-chip ground are used in this design to enhance the antenna gain and reduce the antenna size. The proposed antenna achieves a maximum gain of 8 dBi with a -10 dB bandwidth of 4 GHz. The peak antenna efficiency is 96.7% and the half-power-beamwidth is 72° and 92° in the E-and H-plane respectively. Moreover, the chip size of the presented antenna is 700 μm × 1250 μm.\",\"PeriodicalId\":6625,\"journal\":{\"name\":\"2015 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP)\",\"volume\":\"131 1\",\"pages\":\"1-3\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMWS-AMP.2015.7324967\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMWS-AMP.2015.7324967","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design of a high gain on-chip antenna for SoC application
A V-band high gain and high efficiency on-chip antenna in a CMOS 0.18-μm process is presented in this work. High resistivity silicon substrate, dielectric resonator and a layer of off-chip ground are used in this design to enhance the antenna gain and reduce the antenna size. The proposed antenna achieves a maximum gain of 8 dBi with a -10 dB bandwidth of 4 GHz. The peak antenna efficiency is 96.7% and the half-power-beamwidth is 72° and 92° in the E-and H-plane respectively. Moreover, the chip size of the presented antenna is 700 μm × 1250 μm.
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