0.005mm2 8.5 enob14.9 fJ/反步SAR ADC的设计

Yuan Ma, Xuecheng Wang, Milin Zhang
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引用次数: 0

摘要

本文提出了一种微分方程。采用40nm CMOS技术的5kS/s、300nW、8位逐次逼近寄存器(SAR)模数转换器(ADC),其硅面积为$0.005\ mathm {m}\ mathm {m}^{2}$。提出了一种计算电容失配误差和寄生效应对多结构比较和面积优化性能影响的算法。该ADC在62时的测量FOM为14.9fJ/c-s。5kS/s,有效比特数(ENoB)为8。实现了63.34 dB的无杂散动态范围(SFDR)和60.9 dB的总谐波失真(THD)。
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Design of a 0.005mm2 8.5ENoB 14.9 fJ/conv-step SAR ADC for Biomedical Application
This paper presents a differential 62. 5kS/s, 300nW,8bit successive approximation register (SAR) analog-to-digital converters (ADC) in 40nm CMOS technology occupying a silicon area of $0.005\mathrm{m}\mathrm{m}^{2}$. An algorithm that calculates the impact of capacitor mismatch errors and parasitic effects on performance for multi-structure comparison and area optimization has been proposed. The measured FOM of the proposed ADC is 14.9fJ/c-s at 62. 5kS/s with Effective number of bits (ENoB) of 8. 3bits, spurious free dynamic range (SFDR) of 63.34 dB and total harmonic distortion (THD) of 60.9 dB are achieved.
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