{"title":"第5部分概述:处理器","authors":"S. Rusu, Sonia Leon","doi":"10.1109/ISSCC.2010.5434032","DOIUrl":null,"url":null,"abstract":"Processors have long been the leading edge of integration and process technology and this year's papers emphatically demonstrate that this is still the case. This year's crop of processors exhibit astounding increases in chip integration levels with more cores, special-function units and huge increases in the bandwidth of both on- and off-die interconnect. Emerging markets combine the attributes of network processors (many-threaded low-power cores) and server processors (large cores with virtualization and RAS). Higher levels of memory integration are achieved by using embedded DRAM in these large processors to support the higher-bandwidth demands of throughput computing. The challenges of managing the dramatic growth in dynamic power and leakage (if all integrated components were allowed to activate simultaneously) are addressed with a variety of innovative power management methods such as on-die gating and multiple voltage and frequency domains. Moore's law continues as the first 32nm processors from Intel and AMD are described, together with the latest implementation of the POWER and SPARC architectures.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"27 1","pages":"94-95"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Session 5 overview: Processors\",\"authors\":\"S. Rusu, Sonia Leon\",\"doi\":\"10.1109/ISSCC.2010.5434032\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Processors have long been the leading edge of integration and process technology and this year's papers emphatically demonstrate that this is still the case. This year's crop of processors exhibit astounding increases in chip integration levels with more cores, special-function units and huge increases in the bandwidth of both on- and off-die interconnect. Emerging markets combine the attributes of network processors (many-threaded low-power cores) and server processors (large cores with virtualization and RAS). Higher levels of memory integration are achieved by using embedded DRAM in these large processors to support the higher-bandwidth demands of throughput computing. The challenges of managing the dramatic growth in dynamic power and leakage (if all integrated components were allowed to activate simultaneously) are addressed with a variety of innovative power management methods such as on-die gating and multiple voltage and frequency domains. Moore's law continues as the first 32nm processors from Intel and AMD are described, together with the latest implementation of the POWER and SPARC architectures.\",\"PeriodicalId\":6418,\"journal\":{\"name\":\"2010 IEEE International Solid-State Circuits Conference - (ISSCC)\",\"volume\":\"27 1\",\"pages\":\"94-95\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Solid-State Circuits Conference - (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2010.5434032\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2010.5434032","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Processors have long been the leading edge of integration and process technology and this year's papers emphatically demonstrate that this is still the case. This year's crop of processors exhibit astounding increases in chip integration levels with more cores, special-function units and huge increases in the bandwidth of both on- and off-die interconnect. Emerging markets combine the attributes of network processors (many-threaded low-power cores) and server processors (large cores with virtualization and RAS). Higher levels of memory integration are achieved by using embedded DRAM in these large processors to support the higher-bandwidth demands of throughput computing. The challenges of managing the dramatic growth in dynamic power and leakage (if all integrated components were allowed to activate simultaneously) are addressed with a variety of innovative power management methods such as on-die gating and multiple voltage and frequency domains. Moore's law continues as the first 32nm processors from Intel and AMD are described, together with the latest implementation of the POWER and SPARC architectures.