H. Odagiri, N. Takahashi, T. Shidei, K. Takeshita, Y. Kumagai
{"title":"用于622 Mbps ATM单元处理的新CAM宏","authors":"H. Odagiri, N. Takahashi, T. Shidei, K. Takeshita, Y. Kumagai","doi":"10.1109/CICC.1996.510504","DOIUrl":null,"url":null,"abstract":"A CAM macro for 622 Mbps ATM cell processing has been developed with two built-in circuits, the idle word detection circuit and the multiple hit detection circuit. The macro is fabricated in a standard 0.5 /spl mu/m 3 layer CMOS technology, 40 MHz operation and 70 mW power dissipation with 3.3 V power supply has been confirmed.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"150 1","pages":"21-24"},"PeriodicalIF":0.0000,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A new CAM macro for 622 Mbps ATM cell processing\",\"authors\":\"H. Odagiri, N. Takahashi, T. Shidei, K. Takeshita, Y. Kumagai\",\"doi\":\"10.1109/CICC.1996.510504\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CAM macro for 622 Mbps ATM cell processing has been developed with two built-in circuits, the idle word detection circuit and the multiple hit detection circuit. The macro is fabricated in a standard 0.5 /spl mu/m 3 layer CMOS technology, 40 MHz operation and 70 mW power dissipation with 3.3 V power supply has been confirmed.\",\"PeriodicalId\":74515,\"journal\":{\"name\":\"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference\",\"volume\":\"150 1\",\"pages\":\"21-24\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-05-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1996.510504\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1996.510504","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A CAM macro for 622 Mbps ATM cell processing has been developed with two built-in circuits, the idle word detection circuit and the multiple hit detection circuit. The macro is fabricated in a standard 0.5 /spl mu/m 3 layer CMOS technology, 40 MHz operation and 70 mW power dissipation with 3.3 V power supply has been confirmed.
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