Jianhua Xu, Anni Wang, Jun He, X. Jing, Ziying Zhang, Beichao Zhang
{"title":"14nm金属栅极薄膜堆的发展与挑战","authors":"Jianhua Xu, Anni Wang, Jun He, X. Jing, Ziying Zhang, Beichao Zhang","doi":"10.1109/CSTIC.2017.7919796","DOIUrl":null,"url":null,"abstract":"As IC technology advances to 16/14 nm and beyond, FinFET architecture with advantage of excellent leakage performance becomes main stream in IC industry. However, it also brings big challenges for integration and processes due to its very aggressive structure and profile, CD shrinkage, shadow effect and gap-fill difficulty. In this work, atomic layer deposition (ALD) metal films, including TaN, TiN (TiSiN), TiAl and CVD W, were studied for replacement metal gate application. Challenges of step coverage & gap-fill, loading effect and tunable range of work function will be discussed and addressed. Thickness of high K capping layer (TiN or TaN), work function metal (TiN & TiAl), W barrier layer (TiN) all show strong effect on N/P MOS device Vt, and more than 300 mv tunable range of work function can be achieved. Besides, higher Al : Ti ratio process, interfacial special treatment between TiAl & W barrier TiN and different W process can lower down NMOS Vt. At the last, ALD and CVD process ensure good gap-fill performance when CD opening is larger than 5nm (aspect ratio is about 20∶1).","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"30 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"14nm metal gate film stack development and challenges\",\"authors\":\"Jianhua Xu, Anni Wang, Jun He, X. Jing, Ziying Zhang, Beichao Zhang\",\"doi\":\"10.1109/CSTIC.2017.7919796\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As IC technology advances to 16/14 nm and beyond, FinFET architecture with advantage of excellent leakage performance becomes main stream in IC industry. However, it also brings big challenges for integration and processes due to its very aggressive structure and profile, CD shrinkage, shadow effect and gap-fill difficulty. In this work, atomic layer deposition (ALD) metal films, including TaN, TiN (TiSiN), TiAl and CVD W, were studied for replacement metal gate application. Challenges of step coverage & gap-fill, loading effect and tunable range of work function will be discussed and addressed. Thickness of high K capping layer (TiN or TaN), work function metal (TiN & TiAl), W barrier layer (TiN) all show strong effect on N/P MOS device Vt, and more than 300 mv tunable range of work function can be achieved. Besides, higher Al : Ti ratio process, interfacial special treatment between TiAl & W barrier TiN and different W process can lower down NMOS Vt. At the last, ALD and CVD process ensure good gap-fill performance when CD opening is larger than 5nm (aspect ratio is about 20∶1).\",\"PeriodicalId\":6846,\"journal\":{\"name\":\"2017 China Semiconductor Technology International Conference (CSTIC)\",\"volume\":\"30 1\",\"pages\":\"1-3\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 China Semiconductor Technology International Conference (CSTIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSTIC.2017.7919796\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 China Semiconductor Technology International Conference (CSTIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSTIC.2017.7919796","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
14nm metal gate film stack development and challenges
As IC technology advances to 16/14 nm and beyond, FinFET architecture with advantage of excellent leakage performance becomes main stream in IC industry. However, it also brings big challenges for integration and processes due to its very aggressive structure and profile, CD shrinkage, shadow effect and gap-fill difficulty. In this work, atomic layer deposition (ALD) metal films, including TaN, TiN (TiSiN), TiAl and CVD W, were studied for replacement metal gate application. Challenges of step coverage & gap-fill, loading effect and tunable range of work function will be discussed and addressed. Thickness of high K capping layer (TiN or TaN), work function metal (TiN & TiAl), W barrier layer (TiN) all show strong effect on N/P MOS device Vt, and more than 300 mv tunable range of work function can be achieved. Besides, higher Al : Ti ratio process, interfacial special treatment between TiAl & W barrier TiN and different W process can lower down NMOS Vt. At the last, ALD and CVD process ensure good gap-fill performance when CD opening is larger than 5nm (aspect ratio is about 20∶1).