Spartan 6 FPGA implementation of 2D-discrete wavelet transform in Verilog HDL

The paper gives us, a brief account of the design of 2D - discrete wavelet transform (DWT) implemented in VLSI architecture using Verilog HDL which achieves high speed computation. The main motive behind the development of the architecture is on giving efficient hardware utilization along with high operating speed and less number of clock cycles. To verify the proposed scheme, 2D DWT is applied on a grey image of size 128*128 to get all the four components (average, diagonal, horizontal and vertical), this wavelet decomposition is verified and obtained in Xilinx 14.2 version software using Verilog HDL; circuit is planned, modelled (simulated) in Verilog HDL, and finally the result is validated in FPGA Spartan 6 to get the output 2D-DWT computed image back. This is a single chip implementation where discrete wavelet transform can be used in VLSI design more efficiently than other transform. It is depicted that the operation carried out with specified processing speed of the designed architecture based on the proposed scheme is good than those of the other architectures designed using other existing schemes, and it has less hardware utilization.