A dividerless reference-sampling RF PLL with −253.5dB jitter FOM and <-67dBc Reference Spurs

In the recent past, there have been exciting advances in dividerless PLLs, such as sub-sampling PLLs (SSPLLs) [1,2] and injection-locked clock multipliers (ILCMs) [3] that substantially reduce loop noise to cross the −250dB jitter-power figure-of-merit (FOM,) barrier. However, there exists a fundamental trade-off between FOM, and reference spurs in PLLs, although the mechanisms vary across architectures. Narrow PLL bandwidths are necessary for reducing spurs through filtering, but this can conflict with the optimal bandwidth for jitter. In SSPLLs, buffers, isolating the VCO from the sub-sampled phase detector (SSPD) (Fig. 15.7.1), reduce spurs at the expense of noise and power consumption. Smaller sample capacitances in the SSPD reduce spurs generated by mismatch-induced charge sharing, charge injection, and tank frequency modulation at the expense of increased kT/C noise. Consequently, the SSPLL of [2] achieves spur <-80dBc by using isolation buffers, a small sample capacitance (and another DLL-based technique) but exhibits an FOM, of −244.6dB. In the SSPLL of [1], the elimination of this isolation buffer and the use of a larger capacitance results in a better FOM, of −252dB but a spur of −56dBc. The ILCM in [3] operates with large injection to enable locking to a high multiple of the reference, but this degrades spurs. The absence of noisy loop components yields a very low, but large injection leads to a spur of −43dBc. Also, ILCMs do not feature explicit phase detectors, limiting the optimization of loop dynamics.