等效检验中SAT与bdd的关系

S. Reda, R. Drechsler, A. Orailoglu
{"title":"等效检验中SAT与bdd的关系","authors":"S. Reda, R. Drechsler, A. Orailoglu","doi":"10.1109/ISQED.2002.996778","DOIUrl":null,"url":null,"abstract":"State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on binary decision diagrams (BDDs) and SAT (Boolean satisfiability) solvers. In this paper, we study the relation between the two procedures and show how the number of backtracks obtained in the Davis-Putnam (DP) procedure is linked to the number of paths in the BDD. We utilize this relation to devise a method that uses BDD variable ordering techniques to run the DP procedure. Experimental results confirm that the proposed method results in a dramatic decrease in the number of backtracks and in the time needed to prove the Boolean satisfiability problem as well.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":"{\"title\":\"On the relation between SAT and BDDs for equivalence checking\",\"authors\":\"S. Reda, R. Drechsler, A. Orailoglu\",\"doi\":\"10.1109/ISQED.2002.996778\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on binary decision diagrams (BDDs) and SAT (Boolean satisfiability) solvers. In this paper, we study the relation between the two procedures and show how the number of backtracks obtained in the Davis-Putnam (DP) procedure is linked to the number of paths in the BDD. We utilize this relation to devise a method that uses BDD variable ordering techniques to run the DP procedure. Experimental results confirm that the proposed method results in a dramatic decrease in the number of backtracks and in the time needed to prove the Boolean satisfiability problem as well.\",\"PeriodicalId\":20510,\"journal\":{\"name\":\"Proceedings International Symposium on Quality Electronic Design\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"35\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings International Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2002.996778\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2002.996778","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 35

摘要

最先进的验证工具是基于布尔公式的有效操作。传统的操作技术是基于二进制决策图(bdd)和布尔可满足性(SAT)求解器。在本文中,我们研究了这两个过程之间的关系,并说明了在Davis-Putnam (DP)过程中得到的回溯数是如何与BDD中的路径数联系起来的。我们利用这种关系设计了一种使用BDD变量排序技术来运行DP过程的方法。实验结果表明,该方法大大减少了回溯的次数,也缩短了证明布尔可满足性问题所需的时间。
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On the relation between SAT and BDDs for equivalence checking
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on binary decision diagrams (BDDs) and SAT (Boolean satisfiability) solvers. In this paper, we study the relation between the two procedures and show how the number of backtracks obtained in the Davis-Putnam (DP) procedure is linked to the number of paths in the BDD. We utilize this relation to devise a method that uses BDD variable ordering techniques to run the DP procedure. Experimental results confirm that the proposed method results in a dramatic decrease in the number of backtracks and in the time needed to prove the Boolean satisfiability problem as well.
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