{"title":"基于CNRZ-5的28nm芯片33.33 Gb/s线引脚效率1.06 pJ/bit有线收发器","authors":"Ming-Shiang Lai, Genge Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi","doi":"10.1016/j.mejo.2022.105628","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":18617,"journal":{"name":"Microelectron. J.","volume":"42 1","pages":"105628"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS\",\"authors\":\"Ming-Shiang Lai, Genge Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi\",\"doi\":\"10.1016/j.mejo.2022.105628\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\",\"PeriodicalId\":18617,\"journal\":{\"name\":\"Microelectron. J.\",\"volume\":\"42 1\",\"pages\":\"105628\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectron. J.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1016/j.mejo.2022.105628\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectron. J.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1016/j.mejo.2022.105628","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0