用于高级互连的直接蚀刻Cu表征

L. Wen, F. Yamashita, B. Tang, K. Croes, S. Tahara, Keiichi Shimoda, Takeru Maeshiro, E. Nishimura, F. Lazzarino, I. Ciofi, J. Bommels, Z. Tokei
{"title":"用于高级互连的直接蚀刻Cu表征","authors":"L. Wen, F. Yamashita, B. Tang, K. Croes, S. Tahara, Keiichi Shimoda, Takeru Maeshiro, E. Nishimura, F. Lazzarino, I. Ciofi, J. Bommels, Z. Tokei","doi":"10.1109/IITC-MAM.2015.7325613","DOIUrl":null,"url":null,"abstract":"Cu wires patterning by direct etch methods is investigated at 300mm wafer level. Cross-sectional sidewall profiles with tapering angles around 74.5° are obtained with a mid-line width of 44 nm, which paves the way to further scaling of this technique. Lower resistivity is demonstrated with respect to conventional Cu damascene process, with low leakage current between adjacent Cu lines. An in-situ 10nm SiN cap is deposited as a passivation to enable electrical and reliability tests. The electromigration (EM) characterization shows promising reliability performance of the direct etched Cu wires.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"28 1","pages":"173-176"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Direct etched Cu characterization for advanced interconnects\",\"authors\":\"L. Wen, F. Yamashita, B. Tang, K. Croes, S. Tahara, Keiichi Shimoda, Takeru Maeshiro, E. Nishimura, F. Lazzarino, I. Ciofi, J. Bommels, Z. Tokei\",\"doi\":\"10.1109/IITC-MAM.2015.7325613\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Cu wires patterning by direct etch methods is investigated at 300mm wafer level. Cross-sectional sidewall profiles with tapering angles around 74.5° are obtained with a mid-line width of 44 nm, which paves the way to further scaling of this technique. Lower resistivity is demonstrated with respect to conventional Cu damascene process, with low leakage current between adjacent Cu lines. An in-situ 10nm SiN cap is deposited as a passivation to enable electrical and reliability tests. The electromigration (EM) characterization shows promising reliability performance of the direct etched Cu wires.\",\"PeriodicalId\":6514,\"journal\":{\"name\":\"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)\",\"volume\":\"28 1\",\"pages\":\"173-176\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC-MAM.2015.7325613\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC-MAM.2015.7325613","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

摘要

在300mm晶圆水平上研究了直接蚀刻方法的铜线图案。获得了锥度约为74.5°的横截面侧壁轮廓,中线宽度为44 nm,为进一步扩展该技术铺平了道路。与传统的铜腐蚀工艺相比,其电阻率更低,相邻铜线之间的漏电流更小。原位沉积10nm的SiN帽作为钝化,以进行电气和可靠性测试。电迁移(EM)表征表明,直接蚀刻铜线具有良好的可靠性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Direct etched Cu characterization for advanced interconnects
Cu wires patterning by direct etch methods is investigated at 300mm wafer level. Cross-sectional sidewall profiles with tapering angles around 74.5° are obtained with a mid-line width of 44 nm, which paves the way to further scaling of this technique. Lower resistivity is demonstrated with respect to conventional Cu damascene process, with low leakage current between adjacent Cu lines. An in-situ 10nm SiN cap is deposited as a passivation to enable electrical and reliability tests. The electromigration (EM) characterization shows promising reliability performance of the direct etched Cu wires.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
High-voltage monolithic 3D capacitors based on through-silicon-via technology Wafer level metallic bonding: Voiding mechanisms in copper layers A flexible top metal structure to improve ultra low-k reliability Nanostructured material formation for beyond Si devices Ni silicides formation: Use of Ge and Pt to study the diffusing species, lateral growth and relaxation mechanisms
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1