用于模拟/数字GaAs asic的正常关闭过程

Didier Meignant
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引用次数: 2

摘要

飞利浦研究实验室开发的一种增强模式工艺可通过飞利浦微波Limeil的铸造服务获得。该工艺不仅适用于纯数字电路,而且适用于低成本、超低功耗、高集成度的模拟和模数混合功能。本文介绍了一种采用PNL/LEP技术设计制作的GPS集成前端系统。这个3芯片接收器包括一个集成的VCO,放大器,混频器,相位频率比较器,2位ADC,寄存器和几个预量器。与混合实现相比,该系统的出色性能被认为会导致射频接收器的价格大幅降低。
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A normally-off process for analogue/digital GaAs ASICs

An enhancement mode process developed by Philips Research Labs is available through foundry service at Philips Microwave Limeil. This process is meant to address not only purely digital circuits, but also low-cost, ultra low power analogue and analogue-digital mixed functions with high integration density. In this article, an integrated GPS front-end, designed and fabricated by PNL/LEP, is described. This 3-chip receiver includes an integrated VCO, amplifiers, a mixer, a phase frequency comparator, a 2-bit ADC, registers and several prescalers. The outstanding performance measured on this system is believed to lead to a drastic price reduction of the RF receiver, compared with an hybrid implementation.

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