Device modelling of bendable MOS transistors

This paper presents the directions for computer aided design, modelling and simulation of bendable MOSFET transistors towards futuristic bendable ICs. In order to compensate the bending stress a generalised geometry variation is discussed. Based on drain-current and threshold-voltage parameters varying under the bending stress, a Verilog-A compact model is proposed and describes I-V characteristics of a MOSFET in a standard 0.18-μm CMOS technology. This model has been compiled into Cadence environment to predict value and orientation of the bending stress. The proposed model validates against macro-model simulation results, and agrees for both the electron and hole conduction. It has been found that there is significant performance advantage in process-induced uniaxial stressed n-MOSFET, exhibiting a smaller drain-current variation and thresh old voltage shift by monitoring the bending stress and changing the supply voltage.