Pub Date : 2016-08-11DOI: 10.1109/ISCAS.2016.7527328
Soroush Haeri, Qingye Ding, Zhida Li, L. Trajković
Network visualization enables support and deployment of new services and applications that the current Internet architecture is unable to support. Virtual Network Embedding (VNE) problem that addresses efficient mapping of virtual network elements onto a physical infrastructure (substrate network) is one of the main challenges in network virtualization. The Global Resource Capacity (GRC) is a VNE algorithm that utilizes for virtual link mapping a modified version of Dijkstra's shortest path algorithm. In this paper, we propose the GRC-M algorithm that utilizes the Multicommodity Flow (MCF) algorithm. MCF enables path splitting and yields to higher substrate resource utilizations. Simulation results show that MCF significantly enhances performance of the GRC algorithm.
{"title":"Global resource capacity algorithm with path splitting for virtual network embedding","authors":"Soroush Haeri, Qingye Ding, Zhida Li, L. Trajković","doi":"10.1109/ISCAS.2016.7527328","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527328","url":null,"abstract":"Network visualization enables support and deployment of new services and applications that the current Internet architecture is unable to support. Virtual Network Embedding (VNE) problem that addresses efficient mapping of virtual network elements onto a physical infrastructure (substrate network) is one of the main challenges in network virtualization. The Global Resource Capacity (GRC) is a VNE algorithm that utilizes for virtual link mapping a modified version of Dijkstra's shortest path algorithm. In this paper, we propose the GRC-M algorithm that utilizes the Multicommodity Flow (MCF) algorithm. MCF enables path splitting and yields to higher substrate resource utilizations. Simulation results show that MCF significantly enhances performance of the GRC algorithm.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"70 1","pages":"666-669"},"PeriodicalIF":0.0,"publicationDate":"2016-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85722984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
PUF is a security primitive that exploits the fact that no two ICs are exactly the same. To verify a new PUF design, several metrics including uniqueness, reliability, and randomness must be evaluated, which requires various resources and a long set-up time. In this live demonstration, we have developed an automatically evaluation platform for the PUF design. To the authors' best knowledge, this is the first automatic evaluation platform for the PUF test. The evaluation platform can be used for both FPGA and ASCI PUF testing.
{"title":"Live demonstration: An automatic evaluation platform for physical unclonable function test","authors":"Yijun Cui, Chenghua Wang, Weiqiang Liu, Máire O’Neill","doi":"10.1109/ISCAS.2016.7539068","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539068","url":null,"abstract":"PUF is a security primitive that exploits the fact that no two ICs are exactly the same. To verify a new PUF design, several metrics including uniqueness, reliability, and randomness must be evaluated, which requires various resources and a long set-up time. In this live demonstration, we have developed an automatically evaluation platform for the PUF design. To the authors' best knowledge, this is the first automatic evaluation platform for the PUF test. The evaluation platform can be used for both FPGA and ASCI PUF testing.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"269 1","pages":"2377-2377"},"PeriodicalIF":0.0,"publicationDate":"2016-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77460992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-11DOI: 10.1109/ISCAS.2016.7538963
Kleanthis Papachatzopoulos, I. Kouretas, Vassilis Paliouras
In this paper we investigate the impact of intra- and inter-die variations on the delay sensitivity of certain Residue Number System (RNS) arithmetic circuits in comparison to ordinary binary arithmetic logic. The timing yield of systems that contain multiply-add units (MAC) is of great importance since they dominate important applications such as digital signal processing. Specifically, we employ two different delay models for the estimation of delay distributions of RNS and binary MAC architectures. Our analysis quantitatively proves that RNS MAC architectures that use bases of the form {2n - 1, 2n, 2n + 1} demonstrate better normalized delay variation than binary MAC architectures to characterize both their static timing behaviour and the timing behaviour taking into account the sensitizable paths. Furthermore, it is shown that certain simplified RNS MAC architectures outperform conventional RNS MAC architectures in terms of the μ + α · σ delay variation metric.
{"title":"Dynamic delay variation behaviour of RNS multiply-add architectures","authors":"Kleanthis Papachatzopoulos, I. Kouretas, Vassilis Paliouras","doi":"10.1109/ISCAS.2016.7538963","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7538963","url":null,"abstract":"In this paper we investigate the impact of intra- and inter-die variations on the delay sensitivity of certain Residue Number System (RNS) arithmetic circuits in comparison to ordinary binary arithmetic logic. The timing yield of systems that contain multiply-add units (MAC) is of great importance since they dominate important applications such as digital signal processing. Specifically, we employ two different delay models for the estimation of delay distributions of RNS and binary MAC architectures. Our analysis quantitatively proves that RNS MAC architectures that use bases of the form {2n - 1, 2n, 2n + 1} demonstrate better normalized delay variation than binary MAC architectures to characterize both their static timing behaviour and the timing behaviour taking into account the sensitizable paths. Furthermore, it is shown that certain simplified RNS MAC architectures outperform conventional RNS MAC architectures in terms of the μ + α · σ delay variation metric.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"17 1","pages":"1978-1981"},"PeriodicalIF":0.0,"publicationDate":"2016-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91218155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-11DOI: 10.1109/ISCAS.2016.7527330
Xi Zhang, Chi K. Tse
As renewable energy plants are becoming more widely accessible, one trend of power grids' evolution is decentralization which poses many challenges for grid management. In this paper, we propose a generator allocation method, based on community structure detection, for placing decentralized generators. We take node-generator distance (DG) as an indicator of optimal generators' locations and the underlying community structure is detected with a series of iterating steps. Simulation results show that our method can effectively achieve satisfying allocation solutions as well as enhance the robustness of power systems.
{"title":"An effective generator-allocating method to enhance the robustness of power grid","authors":"Xi Zhang, Chi K. Tse","doi":"10.1109/ISCAS.2016.7527330","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527330","url":null,"abstract":"As renewable energy plants are becoming more widely accessible, one trend of power grids' evolution is decentralization which poses many challenges for grid management. In this paper, we propose a generator allocation method, based on community structure detection, for placing decentralized generators. We take node-generator distance (DG) as an indicator of optimal generators' locations and the underlying community structure is detected with a series of iterating steps. Simulation results show that our method can effectively achieve satisfying allocation solutions as well as enhance the robustness of power systems.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"64 1","pages":"674-677"},"PeriodicalIF":0.0,"publicationDate":"2016-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84363322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The physical unclonable function (PUF) produces die-unique responses and is regarded as an emerging security primitive that can be used for authentication of devices. The complexity of a conventional PUF design based on a ring oscillator (RO) is rather high, so limiting its use in many applications. The configurable ring oscillator (CRO) PUF has been advocated as a possible solution to this issue. In this paper, a low hardware complexity CRO PUF design with an enhanced capability to generate a large number of bit responses is proposed; only an inverter and a multiplexer are used in each delay unit. The responses are generated by considering the variation due to fabrication of the logic gates and wires in the CROs. A novel comparison strategy is proposed for the generation of the responses. The proposed PUF design is implemented on Xilinx Spartan-6 FPGAs. These results show that the proposed CRO PUF design has good uniqueness; moreover, it is also robust in its operation for the temperature range of −25°C∼85°C.
{"title":"Low-cost configurable ring oscillator PUF with improved uniqueness","authors":"Yijun Cui, Chenghua Wang, Weiqiang Liu, Yifei Yu, Máire O’Neill, F. Lombardi","doi":"10.1109/ISCAS.2016.7527301","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527301","url":null,"abstract":"The physical unclonable function (PUF) produces die-unique responses and is regarded as an emerging security primitive that can be used for authentication of devices. The complexity of a conventional PUF design based on a ring oscillator (RO) is rather high, so limiting its use in many applications. The configurable ring oscillator (CRO) PUF has been advocated as a possible solution to this issue. In this paper, a low hardware complexity CRO PUF design with an enhanced capability to generate a large number of bit responses is proposed; only an inverter and a multiplexer are used in each delay unit. The responses are generated by considering the variation due to fabrication of the logic gates and wires in the CROs. A novel comparison strategy is proposed for the generation of the responses. The proposed PUF design is implemented on Xilinx Spartan-6 FPGAs. These results show that the proposed CRO PUF design has good uniqueness; moreover, it is also robust in its operation for the temperature range of −25°C∼85°C.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"74 1","pages":"558-561"},"PeriodicalIF":0.0,"publicationDate":"2016-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78338139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-11DOI: 10.1109/ISCAS.2016.7539096
J. Velten, A. Kummert, Daniel Wagner, K. Gałkowski
Increasing miniaturization of electronic systems and nano-technology enables more and more the realization of real time 3-D spatio-temporal signal processing and control systems. However, while stability is well understood for 1-D systems, open problems remain in the higher dimensional case, e.g. for 3D system realizations, especially with respect to computational complexity and thus hardware effort. We propose a basic and thus fast stability test for systems that can be given in a standard 3-D Roesser-like state space model. Most practical systems can be represented in that manner or at least be transformed into an equivalent system so that the test is applicable to most real world problems. The test itself is inspired by passivity assumptions which for example guarantee stability of electrical reactance networks. It represents a sufficient condition for stability and comprises eigenvalue computations of a sum of Gramian matrices of the same size as the system matrix, which leads in this step to the same complexity as a 1-D stability test. The latter can thus also be applied to adaptive systems, where the system matrix is periodically changing.
{"title":"A passivity based stability measure for discrete 3-D IIR system realizations","authors":"J. Velten, A. Kummert, Daniel Wagner, K. Gałkowski","doi":"10.1109/ISCAS.2016.7539096","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7539096","url":null,"abstract":"Increasing miniaturization of electronic systems and nano-technology enables more and more the realization of real time 3-D spatio-temporal signal processing and control systems. However, while stability is well understood for 1-D systems, open problems remain in the higher dimensional case, e.g. for 3D system realizations, especially with respect to computational complexity and thus hardware effort. We propose a basic and thus fast stability test for systems that can be given in a standard 3-D Roesser-like state space model. Most practical systems can be represented in that manner or at least be transformed into an equivalent system so that the test is applicable to most real world problems. The test itself is inspired by passivity assumptions which for example guarantee stability of electrical reactance networks. It represents a sufficient condition for stability and comprises eigenvalue computations of a sum of Gramian matrices of the same size as the system matrix, which leads in this step to the same complexity as a 1-D stability test. The latter can thus also be applied to adaptive systems, where the system matrix is periodically changing.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"97 1","pages":"2483-2486"},"PeriodicalIF":0.0,"publicationDate":"2016-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80624973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527354
M. I. Molla, Mahboob Qaosar, K. Hirose
This paper presents an instantaneous pitch estimation method based on data adaptive time domain filtering and multivariate synchrosqueezing transform (SST). The filtering approach is implemented with bivariate empirical mode decomposition (bEMD) using white Gaussian noise (wGn) as the reference signal. The bEMD decomposes speech and wGn together into a finite set of intrinsic mode functions (IMFs). The log-energy distribution of wGn's IMFs is employed to determine the threshold used in filtering. The IMFs of speech signal selected by such pre-filtering method is used to construct time-frequency representation (TFR) with multivariate SST. The frequency components are properly localized in the obtained TFR. Spatial filtering and post-processing are applied to TFR prior to estimate the instantaneous pitch. The experimental results illustrate the noise robustness and superiority of the proposed algorithm.
{"title":"Instantaneous pitch estimation of noisy speech signal with multivariate SST","authors":"M. I. Molla, Mahboob Qaosar, K. Hirose","doi":"10.1109/ISCAS.2016.7527354","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527354","url":null,"abstract":"This paper presents an instantaneous pitch estimation method based on data adaptive time domain filtering and multivariate synchrosqueezing transform (SST). The filtering approach is implemented with bivariate empirical mode decomposition (bEMD) using white Gaussian noise (wGn) as the reference signal. The bEMD decomposes speech and wGn together into a finite set of intrinsic mode functions (IMFs). The log-energy distribution of wGn's IMFs is employed to determine the threshold used in filtering. The IMFs of speech signal selected by such pre-filtering method is used to construct time-frequency representation (TFR) with multivariate SST. The frequency components are properly localized in the obtained TFR. Spatial filtering and post-processing are applied to TFR prior to estimate the instantaneous pitch. The experimental results illustrate the noise robustness and superiority of the proposed algorithm.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"30 1","pages":"770-773"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73468609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527341
Renyuan Zhang, M. Kaneko
A field programmable gate array (FPGA) architecture is developed in this work for implementing multi-valued logics (MVL). The arbitrary function of sixteen-valued logic, which is four-bit equivalent to conventional binary circuitry, can be carried out for approximate computations. The number of devices and interconnections in the proposed FPGA processor are both compacted in contrast to those of the conventional binary FPGAs. To memorize MVL datum statically, a self-refreshing and latch-up analog memory cell with four-bit accuracy is designed in a standard CMOS technology. Eighteen transistors are employed by this memory cell, which is only 37.5% of four sets of static binary memory cells. A 16-to-1 multiplexer is also proposed as the look-up table by using sixteen-valued logic signals for addressing A proof-of-concept FPGA processor is designed with 16 by 16 cell-array, and each cell has a four-bit-equivalent capacity. this manner, the number of transistors in lookup tables for such a scale is reduced to 29% of binary lookup tables. The circuit simulation results are presented for the approximate computations of linearly adding, subtracting, and Gaussian functions.
{"title":"A 16-valued logic FPGA architecture employing analog memory circuit","authors":"Renyuan Zhang, M. Kaneko","doi":"10.1109/ISCAS.2016.7527341","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527341","url":null,"abstract":"A field programmable gate array (FPGA) architecture is developed in this work for implementing multi-valued logics (MVL). The arbitrary function of sixteen-valued logic, which is four-bit equivalent to conventional binary circuitry, can be carried out for approximate computations. The number of devices and interconnections in the proposed FPGA processor are both compacted in contrast to those of the conventional binary FPGAs. To memorize MVL datum statically, a self-refreshing and latch-up analog memory cell with four-bit accuracy is designed in a standard CMOS technology. Eighteen transistors are employed by this memory cell, which is only 37.5% of four sets of static binary memory cells. A 16-to-1 multiplexer is also proposed as the look-up table by using sixteen-valued logic signals for addressing A proof-of-concept FPGA processor is designed with 16 by 16 cell-array, and each cell has a four-bit-equivalent capacity. this manner, the number of transistors in lookup tables for such a scale is reduced to 29% of binary lookup tables. The circuit simulation results are presented for the approximate computations of linearly adding, subtracting, and Gaussian functions.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"51 1","pages":"718-721"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74152507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527168
A. Morgado, R. Fernández, J. M. Rosa
This paper presents the design and implementation of a fourth-order band-pass continuous-time ΣΔ modulator intended for the digitization of radio-frequency signals in software-defined-radio applications. The modulator architecture consists of two Gm-LC resonators with a tunable notch frequency and a 4-bit flash analog-to-digital converter in the forward path and a non-return-to-zero digital-to-analog converter with a finite-impulse-response filter in the feedback path. Both system-level and circuit-level reconfiguration techniques are included in order to allow the modulator to digitize signals placed at different carrier frequencies, from 450MHz to 950MHz. A proper synthesis methodology of the loop-filter coefficients at system level and the use of inverter-based switchable transconductors allow to optimize the performance in terms of robustness to circuit errors, stability and power consumption. The circuit, implemented in 65-nm CMOS, can digitise signals with up to 57-dB SNDR within a 40-MHz bandwidth, with an adaptive power dissipation of 16.7-to-22.8 mW and a programmable 1.2/2GHz clock rate1.
本文介绍了一种四阶带通连续时间ΣΔ调制器的设计和实现，用于软件定义无线电应用中射频信号的数字化。调制器架构由两个Gm-LC谐振器组成，其陷波频率可调，前向路径为一个4位闪存模数转换器，反馈路径为一个非归零数模转换器，具有有限脉冲响应滤波器。包括系统级和电路级重构技术，以允许调制器数字化放置在不同载波频率的信号，从450MHz到950MHz。系统级环路滤波器系数的适当综合方法和基于逆变器的可切换晶体管的使用，可以在电路误差、稳定性和功耗方面的鲁棒性方面优化性能。该电路采用65纳米CMOS实现，可在40 mhz带宽内实现高达57 db SNDR的信号数字化，自适应功耗为16.7至22.8 mW，时钟速率可编程为1.2/2GHz 1。
{"title":"Design of a power-efficient widely-programmable Gm-LC band-pass sigma-delta modulator for SDR","authors":"A. Morgado, R. Fernández, J. M. Rosa","doi":"10.1109/ISCAS.2016.7527168","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527168","url":null,"abstract":"This paper presents the design and implementation of a fourth-order band-pass continuous-time ΣΔ modulator intended for the digitization of radio-frequency signals in software-defined-radio applications. The modulator architecture consists of two Gm-LC resonators with a tunable notch frequency and a 4-bit flash analog-to-digital converter in the forward path and a non-return-to-zero digital-to-analog converter with a finite-impulse-response filter in the feedback path. Both system-level and circuit-level reconfiguration techniques are included in order to allow the modulator to digitize signals placed at different carrier frequencies, from 450MHz to 950MHz. A proper synthesis methodology of the loop-filter coefficients at system level and the use of inverter-based switchable transconductors allow to optimize the performance in terms of robustness to circuit errors, stability and power consumption. The circuit, implemented in 65-nm CMOS, can digitise signals with up to 57-dB SNDR within a 40-MHz bandwidth, with an adaptive power dissipation of 16.7-to-22.8 mW and a programmable 1.2/2GHz clock rate1.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"58 1","pages":"53-56"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75409299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-22DOI: 10.1109/ISCAS.2016.7527357
Taehee Lee, JongWon Yi, Joon-Sung Yang
Clock power is a significant portion of chip power in System-on-chip (SoC). Applying Multi-bit flip-flop (MBFF) is capable of providing attractive solution to reduce clock power. To our best knowledge, this is the first work in the literature that considers multi-corner and multi-mode (MCMM) timing constraint for the MBFF generation. This proposed method is applied to five industrial digital intellectual property (IP) blocks of state-of-the-art System-on-chip (SoC). Experimental results show that our proposed MBFF generation algorithm achieves 22% clock power reduction.
{"title":"Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint","authors":"Taehee Lee, JongWon Yi, Joon-Sung Yang","doi":"10.1109/ISCAS.2016.7527357","DOIUrl":"https://doi.org/10.1109/ISCAS.2016.7527357","url":null,"abstract":"Clock power is a significant portion of chip power in System-on-chip (SoC). Applying Multi-bit flip-flop (MBFF) is capable of providing attractive solution to reduce clock power. To our best knowledge, this is the first work in the literature that considers multi-corner and multi-mode (MCMM) timing constraint for the MBFF generation. This proposed method is applied to five industrial digital intellectual property (IP) blocks of state-of-the-art System-on-chip (SoC). Experimental results show that our proposed MBFF generation algorithm achieves 22% clock power reduction.","PeriodicalId":6546,"journal":{"name":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"782-785"},"PeriodicalIF":0.0,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75849773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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