Effective Implementation of "Kuznyechik" Block Cipher on FPGA with OpenCL Platform

Growing amounts of information transmitted over computer networks require high-performance implementations of cryptographic functions. At speeds above 10 Gbit/s, it is no longer possible to use the CPU for cryptographic packet processing. The ideal solution is to shift the task of cryptographic packet processing to FPGA. This requires a high-performance, and preferably low-cost implementation of cryptographic functions. Also, since the development of such accelerators in hardware description languages is still quite an expensive task, the programming language OpenCL, supported by all major FPGA manufacturers, can be used to reduce development time. This paper presents a high-performance and low-cost FPGA implementation of the block cipher Kuznyechik in OpenCL for FPGA. The resulting implementation is able to encrypt data at a speed of 41 Gbit/s on FPGA Arria 10 10AX115S2F45I1SG, while occupying no more than 10% of FPGA resources.