A sub-1V low dropout regulator with improved transient performance for low power digital systems

This paper presents a low-voltage Flipped Voltage Follower (FVF) based output-capacitorless low-dropout (OCL-LDO) regulator. It consists of a transient-enhanced push-pull (TEPP) driving stage to improve the response at low quiescent power. With simple Miller compensation (SMC) and modified damping factor control (DFC) compensation, the regulator permits small compensation capacitance for maintaining circuit stability under different loading conditions whilst increasing the design flexibility. Validated by UMC 65nm CMOS technology, the regulator can support the capacitive load from 100 pF to 3 nF. It delivers a maximum load current of 10 mA with a dropout voltage of 200 mV in 0.9 V supply and a quiescent current of less than 20 μA. The regulator's output voltage stays within 1% of the final steady-state voltage level during load current transitions. Compared with other reported counterparts, it displays reasonable good transient figure-of-merits (FOMs), particularly suitable for low power digital systems.