灵活、高吞吐量的山茶花分组密码结构,保障物联网安全

IF 1.1 4区 计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE IET Computers and Digital Techniques Pub Date : 2021-03-12 DOI:10.1049/cdt2.12025
Bahram Rashidi
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引用次数: 3

摘要

无线通信的进步创造了物联网(IoT)系统的指数级增长。在许多数据敏感型应用中,物联网系统的安全性和隐私性是关键挑战。本文提出了用于物联网应用的Camellia分组密码的高吞吐量和灵活的硬件实现。在所提出的结构中,密码的子块是基于优化电路实现的。所提出的Camellia结构被设计和共享,用于实现加密过程并在两个不同的时间生成一些中间密钥值。这些密码中最复杂的块是替换盒(S-box)。s盒是基于面积优化逻辑电路实现的。Camellia s -box由f28上的场反演和F上的两个仿射变换组成2 .反演运算在复合场F(2)上实现4) 2而不是F的反转这是减少面积消耗的重要因素。在结构中,大量的门由2输入NAND和2输入NOR门来实现,以减少延迟和面积。此外,还提出了Camellia的灵活结构,可以对该密码进行各种配置,以支持128、192和256位的可变密钥大小。在180 nm CMOS技术上,针对不同的密钥尺寸,获得了所提出架构的实现结果。结果显示,与其他相关工作相比,在执行时间、吞吐量和吞吐量/面积方面有所改进。
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Flexible and high-throughput structures of Camellia block cipher for security of the Internet of Things

The advancements in wireless communication have created exponential growth in the Internet of Things (IoT) systems. Security and privacy of the IoT systems are critical challenges in many data-sensitive applications. Herein, high-throughput and flexible hardware implementations of the Camellia block cipher for IoT applications are presented. In the proposed structures, sub-blocks of the ciphers are implemented based on optimised circuits. The proposed structures for Camellia are designed and shared for implementing the encryption process and generating some intermediate key values in the two separate times. The most complex block in these ciphers is the substitution box (S-box). The S-boxes are implemented based on area-optimised logic circuits. The Camellia S-boxes consist of a field inversion over F 2 8 and two affine transformations over F 2 . The inversion operation is implemented over the composite field F ( 2 4 ) 2 instead of an inversion over F 2 8 which is an important factor to reduce area consumption. A large number of gates, in the structure, have been implemented by 2-input NAND and 2-input NOR gates to reduce delay and area. Also, the flexible structure for Camellia that can do various configurations of this cipher to support variable key sizes 128, 192 and 256 bits was proposed. Implementation results of the proposed architectures in 180 nm CMOS technology for different key sizes are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared to the other related works.

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来源期刊
IET Computers and Digital Techniques
IET Computers and Digital Techniques 工程技术-计算机:理论方法
CiteScore
3.50
自引率
0.00%
发文量
12
审稿时长
>12 weeks
期刊介绍: IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test. The key subject areas of interest are: Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation. Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance. Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues. Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware. Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting. Case Studies: emerging applications, applications in industrial designs, and design frameworks.
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