{"title":"一种新型开关数减少的七电平逆变器拓扑结构","authors":"M. Siddique, A. Iqbal, M. Al-Hitmi","doi":"10.1109/IECON43393.2020.9255108","DOIUrl":null,"url":null,"abstract":"This paper aims to improve the power and voltage quality of a new multilevel inverter which contains a smaller number of switches in the specified voltage levels. The single phase of the proposed inverter includes 8 electronic power devices with three dc voltage sources for the seven-level waveforms. Selective harmonic elimination (SHE) technique has been used for the dominant harmonic elimination. The results of the proposed structure with traditional topologies and similar topologies show that, in terms of switch number, driver number, and the total blocking voltage, the proposed structure was superior to the previous versions. This topology is studied by simulations in the environment of PLECS.","PeriodicalId":13045,"journal":{"name":"IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society","volume":"64 3 1","pages":"3285-3290"},"PeriodicalIF":0.0000,"publicationDate":"2020-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A New Seven-Level Inverter Topology with Reduced Switch Number\",\"authors\":\"M. Siddique, A. Iqbal, M. Al-Hitmi\",\"doi\":\"10.1109/IECON43393.2020.9255108\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper aims to improve the power and voltage quality of a new multilevel inverter which contains a smaller number of switches in the specified voltage levels. The single phase of the proposed inverter includes 8 electronic power devices with three dc voltage sources for the seven-level waveforms. Selective harmonic elimination (SHE) technique has been used for the dominant harmonic elimination. The results of the proposed structure with traditional topologies and similar topologies show that, in terms of switch number, driver number, and the total blocking voltage, the proposed structure was superior to the previous versions. This topology is studied by simulations in the environment of PLECS.\",\"PeriodicalId\":13045,\"journal\":{\"name\":\"IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society\",\"volume\":\"64 3 1\",\"pages\":\"3285-3290\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IECON43393.2020.9255108\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IECON43393.2020.9255108","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A New Seven-Level Inverter Topology with Reduced Switch Number
This paper aims to improve the power and voltage quality of a new multilevel inverter which contains a smaller number of switches in the specified voltage levels. The single phase of the proposed inverter includes 8 electronic power devices with three dc voltage sources for the seven-level waveforms. Selective harmonic elimination (SHE) technique has been used for the dominant harmonic elimination. The results of the proposed structure with traditional topologies and similar topologies show that, in terms of switch number, driver number, and the total blocking voltage, the proposed structure was superior to the previous versions. This topology is studied by simulations in the environment of PLECS.