Tailored parallel micro-channel cooling for hot spot mitigation

Modern electronics feature high surface heat fluxes, particularly at localized hot spots, which can be detrimental to chip performance. While techniques have been developed to alleviate these local effects, they are typically advanced solutions using embedded cooling devices. Instead, an effective, less aggressive solution involves the adaptation of traditional micro-channel cooling to the particular thermal profile. An analytical method is developed to determine individual channel flow rates and convective heat transfer through traditional correlations. This results in a simple power law relating passage diameter, D, to hot spot power, q, where D ~ qm. Unfortunately, this method is limited by the form of the empirical correlations, being applicable to only certain ranges of Reynolds numbers and channel sizes. To address this issue, a series of computational simulations has been conducted to select the appropriate power law for typical flow conditions in a micro-channel heat sink. For laminar, developing flow at ReD ~ 100, an empirical fit was generated. At an arbitrary, non-uniform chip power dissipation, the device temperature rises balanced to within less than 5%, even with up to three times more power at local spots.