一个112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX在14nm CMOS

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI:10.1109/ISSCC.2018.8310205

C. Menolfi, M. Braendli, P. Francese, T. Morf, A. Cevrero, M. Kossel, L. Kull, D. Luu, Ilter Özkaya, T. Toifl

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引用次数: 47

摘要

在有线和光通信中对更高数据速率的持续需求导致了100Gb/s+体制的新兴标准[1]。虽然这些标准仍处于定义阶段，但它们将依赖于PAM-4等多级信令以及越来越多的数字信号处理。在可预见的未来，高性能TX将由CMOS DSP前端和高采样率数据转换器组成[2,3]，其设计仍然是一个重大挑战。本文提出了一个112Gb/s的PAM-4 SST Tx，它基于一个四分之一速率56GS/s的8b SST DAC以及一个用于通道均衡的数字8分接FIR滤波器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

The ongoing demand for higher data rates in wireline and optical communications has led to emerging standards in the 100Gb/s+ regime [1]. Although these standards are still in the definition phase they will rely on multi-level signaling such as PAM-4 along with an increasing amount of digital signal processing. In the foreseeable future, a high-performance TX will consist of a CMOS DSP frontend followed by a high sampling rate data converter [2,3], whose design remains a significant challenge. This paper presents a 112Gb/s PAM-4 SST Tx that is based on a quarter-rate 56GS/s 8b SST DAC along with a digital 8-tap FIR filter for channel equalization.

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2018 IEEE International Solid - State Circuits Conference - (ISSCC)

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