Izhikevich脉冲神经元模型在FPGA上的设计与实现

S. Murali, J. Kumar, Jayanth Kumar, R. Bhakthavatchalu
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引用次数: 3

摘要

大脑的基本处理单元是神经元,它们以各种形状和大小相互连接。一个典型的神经元在功能上可以分为三个不同的部分,分别是树突、体细胞和轴突。树突扮演输入装置的角色,收集来自其他神经元的信号并将其传递给躯体。Soma执行非线性操作,即如果输入超过某个阈值,则产生输出信号。输出信号由输出装置轴突接收,轴突将信号传递给其他神经元。这是生物神经元的基本功能。生物神经元模型又称脉冲神经元模型,是对神经元特性的数学描述,用以准确地描述和预测生物过程。于是就有了神经元建模和分析的概念。不同的研究者对第一代、第二代和第三代神经元进行了建模和分析。第三代神经元也被称为尖峰神经元。这项工作的重点是展示由Izhikevich开发的不同类型的尖峰神经元,这些神经元在数学上支持这些特性并与生物神经元相似。这些数学模型的仿真是在MATLAB中完成的。这些尖峰神经元使用Verilog硬件描述语言(HDL)中的数字逻辑电路建模,并在ModelSIM RTL模拟器中进行仿真。然后在Xilinx FPGA中实现该设计并检查其功能。
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Design and implementation of Izhikevich spiking neuron model on FPGA
The elementary processing units in brain are neurons which are connected to each other in many shapes and sizes. A typical neuron can be divided into functionally three distinct parts called Dendrites, Soma and Axon. Dendrites play the role of input device that collect signals from other neurons and transmits them to soma. Soma performs a Non-linear operation, i.e. if input exceeds a certain threshold, an output signal is generated. This output signal is taken over by an output device, the Axon, which delivers the signal to other neurons. This is the basic function of a biological neuron. A biological neuron model which is also known as Spiking Neuron Model is a mathematical description of properties of neuron that is to be designed accurately to describe and predict the biological processes. So there comes the concept of modelling and analysis of neurons. Modelling and analysis of neurons was performed by different researchers on First, Second and Third generation of neurons. The Third generation of neurons are also called as spiking neurons. The focus of this work is to present different types of spiking neurons developed by Izhikevich which mathematically supports the properties and resembles the biological neuron. These mathematical model simulations are done in MATLAB. These spiking neurons are modelled using digital logic circuits in Verilog Hardware Description Language (HDL) and simulated in ModelSIM RTL simulator. The design is then implemented in Xilinx FPGA and checked for the functionality.
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