Pub Date : 2016-08-23DOI: 10.1109/RTEICT.2016.7808203
B. Rani
Depression is considered as a psychosomatic state associated with the soft biometric features. People suffering from depression always behave abnormal. Depression is a clinically proven disorder that can overwhelm a person and his ability to perform even a simple task. Soft biometric provides important information about a person without being enough for their verification because they lack uniqueness. This statement comprises of features which are associated with the psychosomatic state of a person such as feelings, sentiments or brain related disorders like depression. In this paper we have estimated the depression level of each speech signal using I-Vector technique. In our proposed approach first of all we have removed silence from the speech signal then we have extracted features from audio using I-Vector after that split overlapping function is applied to evaluate overlapped audio beats. In the end we have evaluated depression using relationship matrix. We have estimated the depression level of each speaker. This technique has better performance as compared with existing techniques. The overall result has shown that the I-Vector technique has good accuracy to detect depression in audios.
{"title":"I-Vector based depression level estimation technique","authors":"B. Rani","doi":"10.1109/RTEICT.2016.7808203","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7808203","url":null,"abstract":"Depression is considered as a psychosomatic state associated with the soft biometric features. People suffering from depression always behave abnormal. Depression is a clinically proven disorder that can overwhelm a person and his ability to perform even a simple task. Soft biometric provides important information about a person without being enough for their verification because they lack uniqueness. This statement comprises of features which are associated with the psychosomatic state of a person such as feelings, sentiments or brain related disorders like depression. In this paper we have estimated the depression level of each speech signal using I-Vector technique. In our proposed approach first of all we have removed silence from the speech signal then we have extracted features from audio using I-Vector after that split overlapping function is applied to evaluate overlapped audio beats. In the end we have evaluated depression using relationship matrix. We have estimated the depression level of each speaker. This technique has better performance as compared with existing techniques. The overall result has shown that the I-Vector technique has good accuracy to detect depression in audios.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89045006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-08-22DOI: 10.1109/RTEICT.2016.7807780
Ritu, Sushma Jain
Trust is a vital factor, especially for service oriented systems in the area of Information Technology and Security. Several issues have been raised by enterprises and individuals concerning the reliability of the cloud resources. In cloud computing, trust helps the consumer to choose the service of a cloud provider for storing and processing their sensitive information. In this paper, a trust model is proposed which uses Quality of Service parameters (QoS) to evaluate trust. The fuzzy nature of trust has encouraged us to use fuzzy logic to calculate trust value of a provider in cloud environment, thus increasing the effectiveness of the system. QoS parameters such as turnaround time, availability and reliability are taken for trust evaluation.
{"title":"A trust model in cloud computing based on fuzzy logic","authors":"Ritu, Sushma Jain","doi":"10.1109/RTEICT.2016.7807780","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7807780","url":null,"abstract":"Trust is a vital factor, especially for service oriented systems in the area of Information Technology and Security. Several issues have been raised by enterprises and individuals concerning the reliability of the cloud resources. In cloud computing, trust helps the consumer to choose the service of a cloud provider for storing and processing their sensitive information. In this paper, a trust model is proposed which uses Quality of Service parameters (QoS) to evaluate trust. The fuzzy nature of trust has encouraged us to use fuzzy logic to calculate trust value of a provider in cloud environment, thus increasing the effectiveness of the system. QoS parameters such as turnaround time, availability and reliability are taken for trust evaluation.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80657686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-07-29DOI: 10.1007/978-981-10-4741-1_24
Ashish Kumar, Divya Rani, B. Sujatha
{"title":"Time dispersion parameters for single bounce 2D geometrical channel including rain fading effect","authors":"Ashish Kumar, Divya Rani, B. Sujatha","doi":"10.1007/978-981-10-4741-1_24","DOIUrl":"https://doi.org/10.1007/978-981-10-4741-1_24","url":null,"abstract":"","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89864078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-27DOI: 10.1109/RTEICT.2016.7807956
Kanu Goel, Parteek Bhatia
The key for enabling smooth information sharing across channels is the efficient storage of the information in a language independent format so that it can be retrieved across many geographies without having multiple corpus. This paper explains how this complex requirement can be solved by using UNL. In the paper the architecture and implementation of the UNL interlingua based question answering system is given that is capable enough to handle user queries against a language-independent representation of document. Currently the system solves factoid based questions as where, what, why, which etc using english as source language but later can be extended to other languages once their enconvertors and deconvertors are available. The proposed model is tested on ELOSS documents achieving an accuracy of 82.22%.
{"title":"Information retrieval system using UNL for multilingual question answering","authors":"Kanu Goel, Parteek Bhatia","doi":"10.1109/RTEICT.2016.7807956","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7807956","url":null,"abstract":"The key for enabling smooth information sharing across channels is the efficient storage of the information in a language independent format so that it can be retrieved across many geographies without having multiple corpus. This paper explains how this complex requirement can be solved by using UNL. In the paper the architecture and implementation of the UNL interlingua based question answering system is given that is capable enough to handle user queries against a language-independent representation of document. Currently the system solves factoid based questions as where, what, why, which etc using english as source language but later can be extended to other languages once their enconvertors and deconvertors are available. The proposed model is tested on ELOSS documents achieving an accuracy of 82.22%.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78507519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7807785
P. J. Antony, Prajna Manujesh, N. A. Jnanesh
This review paper explores the attempts made by the numerous authors in the field of material selection. There are ample amounts of works were carried out in the field of materials engineering with data mining approaches. From the literature it is revealed that not much of the work is explored on the classification of advanced composite materials using machine learning approaches.
{"title":"Data mining and machine learning approaches on engineering materials — A review","authors":"P. J. Antony, Prajna Manujesh, N. A. Jnanesh","doi":"10.1109/RTEICT.2016.7807785","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7807785","url":null,"abstract":"This review paper explores the attempts made by the numerous authors in the field of material selection. There are ample amounts of works were carried out in the field of materials engineering with data mining approaches. From the literature it is revealed that not much of the work is explored on the classification of advanced composite materials using machine learning approaches.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74741230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7807891
R. Kumawat, T. Sasamal
Limitations of present complementary metal oxide semiconductor (CMOS) technology are heat dissipation, power dissipation, scaling problem and performance degradation. These problems can be resolved by adopting new emerging technologies like quantum-dot cellular automata (QCA) and reversible logic technology, which provides a new horizon in low power computation. Reversible logic technology handles heat dissipation problem very effectively whereas remaining problems can be easily taken care by QCA. Here, full adder and 4-bit ripple carry adder (RCA) are implemented using Peres gate (PG). QCADesigner tool has been used for designing of Peres gate, full adder and 4-bit RCA. The proposed Peres gate requires 137 cells which covers an area of 0.13μm2 with one clock cycle delay. The proposed full adder is evaluated and achieves 60%, 19.7% and 50% improvement in area, complexity (no. of cells) and delay respectively. Similarly proposed 4-bit RCA gains significant improvement in terms of area, complexity and delay.
{"title":"Design of 1-bit and 4-bit adder using reversible logic in quantum-dot cellular automata","authors":"R. Kumawat, T. Sasamal","doi":"10.1109/RTEICT.2016.7807891","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7807891","url":null,"abstract":"Limitations of present complementary metal oxide semiconductor (CMOS) technology are heat dissipation, power dissipation, scaling problem and performance degradation. These problems can be resolved by adopting new emerging technologies like quantum-dot cellular automata (QCA) and reversible logic technology, which provides a new horizon in low power computation. Reversible logic technology handles heat dissipation problem very effectively whereas remaining problems can be easily taken care by QCA. Here, full adder and 4-bit ripple carry adder (RCA) are implemented using Peres gate (PG). QCADesigner tool has been used for designing of Peres gate, full adder and 4-bit RCA. The proposed Peres gate requires 137 cells which covers an area of 0.13μm2 with one clock cycle delay. The proposed full adder is evaluated and achieves 60%, 19.7% and 50% improvement in area, complexity (no. of cells) and delay respectively. Similarly proposed 4-bit RCA gains significant improvement in terms of area, complexity and delay.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74175979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7808185
R. Prasanth, A. Deshmukh, B. Vignesh, R. Janani
This study deals with the development of vision for vehicle and driver to prevent problems for both vehicle and driver while driving. Wireless communication in car is the booming field of Network communication. An Head-up-Display is developed for calculating the car strategies which help in maintenance and life time of the car to analyze the system with the help of CAN (Controller Area Network) used for communication inside the ECU (Electronic Control Unit) from ELM327 Bluetooth analyzer. And a pulse sensor is connected to the processor to analyze and send immediate signal to the emergency contacts in the time of abnormal conditions of the person while driving. By using Node-Red in the communication will lead the communication easier for the person using and implementing the HUD will lead the maintenance of the system good.
{"title":"An HUD for connected car for maintenance and emergency intimation","authors":"R. Prasanth, A. Deshmukh, B. Vignesh, R. Janani","doi":"10.1109/RTEICT.2016.7808185","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7808185","url":null,"abstract":"This study deals with the development of vision for vehicle and driver to prevent problems for both vehicle and driver while driving. Wireless communication in car is the booming field of Network communication. An Head-up-Display is developed for calculating the car strategies which help in maintenance and life time of the car to analyze the system with the help of CAN (Controller Area Network) used for communication inside the ECU (Electronic Control Unit) from ELM327 Bluetooth analyzer. And a pulse sensor is connected to the processor to analyze and send immediate signal to the emergency contacts in the time of abnormal conditions of the person while driving. By using Node-Red in the communication will lead the communication easier for the person using and implementing the HUD will lead the maintenance of the system good.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74263587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7807987
Dhwani P. Sametriya, Nisarg M. Vasavada, Dipika S. Vasava
With the prevalence of VLSI technology and electronics devices becoming smaller, denser, smarter and long lasting, the research in the field of low voltage applicability and low power consumption is turning omnidirectional among which one direction leads towards the depth of faster and precise clock generation which is achieved on the foundation of PLL. The time has come to break one of the famous Silicon Valley golden rules which states "Higher the clock frequency, Greater the power consumption". Keeping the trivial relationship between power consumption and power dissipation in mind, lowering supply voltages is the most effective method to reduce power consumption. At lower supply voltage, it is challenging to optimize each block of PLL for Low Voltage operations. A Low voltage High Frequency ALF Charge Pump PLL is proposed. It employs a differential Charge pump with an active loop filter to compensate current mismatch and reduces reference spurs. A Voltage Controlled Oscillator is designed with body bias technique providing wide capture range and low power consumption. A D Flip Flop PFD is designed with TSPC dynamic logic to achieve zero or minimum dead zone and is able to detect large phase and frequency difference.
{"title":"Design and simulation of LV PLL with ALF D-charge pump in 90 nm CMOS technology","authors":"Dhwani P. Sametriya, Nisarg M. Vasavada, Dipika S. Vasava","doi":"10.1109/RTEICT.2016.7807987","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7807987","url":null,"abstract":"With the prevalence of VLSI technology and electronics devices becoming smaller, denser, smarter and long lasting, the research in the field of low voltage applicability and low power consumption is turning omnidirectional among which one direction leads towards the depth of faster and precise clock generation which is achieved on the foundation of PLL. The time has come to break one of the famous Silicon Valley golden rules which states \"Higher the clock frequency, Greater the power consumption\". Keeping the trivial relationship between power consumption and power dissipation in mind, lowering supply voltages is the most effective method to reduce power consumption. At lower supply voltage, it is challenging to optimize each block of PLL for Low Voltage operations. A Low voltage High Frequency ALF Charge Pump PLL is proposed. It employs a differential Charge pump with an active loop filter to compensate current mismatch and reduces reference spurs. A Voltage Controlled Oscillator is designed with body bias technique providing wide capture range and low power consumption. A D Flip Flop PFD is designed with TSPC dynamic logic to achieve zero or minimum dead zone and is able to detect large phase and frequency difference.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77608273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7808189
V. Nagendra, S. R. Yedhuraj, T. Subramanyam
Thin Film Transistors (TFTs) are gaining its popularity in all fundamental electronic devices from large diagonal flat display TVs to flexible electronic devices. In this work, the dielectric layer of the TFT, amorphous Silicon Nitride films was fabricated and optimized using Plasma Enhanced Chemical Vapour Deposition (PECVD) technique, using Silane (SiH4) and Ammonia (NH3) as the precursor gases. The optimized process parameters for this thin layer coating had a deposition rate of 63.7 nm at 250oC, 7W RF power and gas flow ratio of 1:3 (SiH4: NH3). Using electrical and optical characterization, the electrical resistance and electronic bandgap of these thin films were found to be 2.71 GΩ and 2.72eV respectively. The semiconductor active layer was chosen to be hydrogenated amorphous silicon (a-Si: H), which was coated using PECVD technique, using SiH4 and H2 as the precursor gases. The chemical composition of a-Si:H coating was confirmed using Raman Spectroscopy. The Gate, Drain and Source materials were chosen to be Aluminium, which was coated using Thermal Evaporation technique and the electrical resistance was measured to be 0.8 Ω. The final TFT constructed using these individual layers, was characterized for its IV characteristics using a semiconductor device analyzer and the values of the current obtained were in Amps. However, the obtained graphs showed a lack of saturation for increased drain voltage values. On further analysis, it was learnt that the performance of this TFT could be further improved by increasing the P-type doping of a-Si: H thin films.
{"title":"Optimization and fabrication of amorphous silicon based TFT","authors":"V. Nagendra, S. R. Yedhuraj, T. Subramanyam","doi":"10.1109/RTEICT.2016.7808189","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7808189","url":null,"abstract":"Thin Film Transistors (TFTs) are gaining its popularity in all fundamental electronic devices from large diagonal flat display TVs to flexible electronic devices. In this work, the dielectric layer of the TFT, amorphous Silicon Nitride films was fabricated and optimized using Plasma Enhanced Chemical Vapour Deposition (PECVD) technique, using Silane (SiH4) and Ammonia (NH3) as the precursor gases. The optimized process parameters for this thin layer coating had a deposition rate of 63.7 nm at 250oC, 7W RF power and gas flow ratio of 1:3 (SiH4: NH3). Using electrical and optical characterization, the electrical resistance and electronic bandgap of these thin films were found to be 2.71 GΩ and 2.72eV respectively. The semiconductor active layer was chosen to be hydrogenated amorphous silicon (a-Si: H), which was coated using PECVD technique, using SiH4 and H2 as the precursor gases. The chemical composition of a-Si:H coating was confirmed using Raman Spectroscopy. The Gate, Drain and Source materials were chosen to be Aluminium, which was coated using Thermal Evaporation technique and the electrical resistance was measured to be 0.8 Ω. The final TFT constructed using these individual layers, was characterized for its IV characteristics using a semiconductor device analyzer and the values of the current obtained were in Amps. However, the obtained graphs showed a lack of saturation for increased drain voltage values. On further analysis, it was learnt that the performance of this TFT could be further improved by increasing the P-type doping of a-Si: H thin films.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81776529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-05-20DOI: 10.1109/RTEICT.2016.7808182
Aishwarya N. Kumar, Anusha Ashok Bijapur, B. Charitha, Kirthi R. Kulkarni, K. Natarajan
Inverters and routers are commonly found in most households today. Through this work we discuss the implementation of a smart inverter i.e a solar charged inverter that uses Wi-Fi technology to engage in a two way communication with the user, informing the user of both, the battery voltage of the inverter as well as run time of the loads which the user chooses to run. Furthermore, wireless control of loads is implemented to increase human comfort. This work uses the MSP430F5529LP microcontroller along with an ESP8266 Wi-Fi module to implement the aforesaid objectives.
{"title":"An IOT based smart inverter","authors":"Aishwarya N. Kumar, Anusha Ashok Bijapur, B. Charitha, Kirthi R. Kulkarni, K. Natarajan","doi":"10.1109/RTEICT.2016.7808182","DOIUrl":"https://doi.org/10.1109/RTEICT.2016.7808182","url":null,"abstract":"Inverters and routers are commonly found in most households today. Through this work we discuss the implementation of a smart inverter i.e a solar charged inverter that uses Wi-Fi technology to engage in a two way communication with the user, informing the user of both, the battery voltage of the inverter as well as run time of the loads which the user chooses to run. Furthermore, wireless control of loads is implemented to increase human comfort. This work uses the MSP430F5529LP microcontroller along with an ESP8266 Wi-Fi module to implement the aforesaid objectives.","PeriodicalId":6527,"journal":{"name":"2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2016-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75976336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：