{"title":"基于光谱跟踪的0.13 μm CMOS数据速率自适应0.622-10Gb /s无电感线性均衡器","authors":"S. Ray, M. Hella","doi":"10.1109/CICC.2015.7338375","DOIUrl":null,"url":null,"abstract":"This paper presents an adaptive equalizer based on dual-loop balancing technique and a third order nested feedback equalizing filter to achieve data rate up to 10Gb/s without using inductors. A spectral balancing circuit adjusts the equalizer boost, while a second servo loop automatically tracks the data rate using self-calibration and re-tunes the filters for optimal equalization. Third order nested feedback is introduced in the equalizing filters to compensate for ~15dB channel loss for a highest data rate of 10Gb/s. Implemented in IBM 0.13-μm CMOS technology, the equalizer maintains an eye opening of 0.26, 0.44 and 0.5UI with BER<;10-12 for 5 Gb/s, 8.5Gb/s and 10Gb/s PRBS31 inputs, respectively. The chip dissipates 130 mW from a 1.2V power supply, while occupying an active area of 0.34 mm2.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"4 3 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 0.622–10Gb/s inductorless adaptive linear equalizer with spectral tracking for data rate adaptation in 0.13-μm CMOS\",\"authors\":\"S. Ray, M. Hella\",\"doi\":\"10.1109/CICC.2015.7338375\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an adaptive equalizer based on dual-loop balancing technique and a third order nested feedback equalizing filter to achieve data rate up to 10Gb/s without using inductors. A spectral balancing circuit adjusts the equalizer boost, while a second servo loop automatically tracks the data rate using self-calibration and re-tunes the filters for optimal equalization. Third order nested feedback is introduced in the equalizing filters to compensate for ~15dB channel loss for a highest data rate of 10Gb/s. Implemented in IBM 0.13-μm CMOS technology, the equalizer maintains an eye opening of 0.26, 0.44 and 0.5UI with BER<;10-12 for 5 Gb/s, 8.5Gb/s and 10Gb/s PRBS31 inputs, respectively. The chip dissipates 130 mW from a 1.2V power supply, while occupying an active area of 0.34 mm2.\",\"PeriodicalId\":6665,\"journal\":{\"name\":\"2015 IEEE Custom Integrated Circuits Conference (CICC)\",\"volume\":\"4 3 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Custom Integrated Circuits Conference (CICC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2015.7338375\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2015.7338375","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.622–10Gb/s inductorless adaptive linear equalizer with spectral tracking for data rate adaptation in 0.13-μm CMOS
This paper presents an adaptive equalizer based on dual-loop balancing technique and a third order nested feedback equalizing filter to achieve data rate up to 10Gb/s without using inductors. A spectral balancing circuit adjusts the equalizer boost, while a second servo loop automatically tracks the data rate using self-calibration and re-tunes the filters for optimal equalization. Third order nested feedback is introduced in the equalizing filters to compensate for ~15dB channel loss for a highest data rate of 10Gb/s. Implemented in IBM 0.13-μm CMOS technology, the equalizer maintains an eye opening of 0.26, 0.44 and 0.5UI with BER<;10-12 for 5 Gb/s, 8.5Gb/s and 10Gb/s PRBS31 inputs, respectively. The chip dissipates 130 mW from a 1.2V power supply, while occupying an active area of 0.34 mm2.