CMOS模拟电路的电路级失配建模和良率优化

Mingjing Chen, A. Orailoglu
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引用次数: 1

摘要

提出了一种构建电路级失配模型并进行良率优化的方法。该方法将统计技术与电路行为的直接调查相结合,在保证足够精度的同时实现了模型简化和计算效率。电路级失配模型可用于性能表征和良率估计,两者都为电路可靠性分析提供重要信息。提出的成品率优化技术包括在可设计参数上构造和细化成品率模型,并保证快速收敛到全局最优设计。在两个代表性电路上的实验结果验证了该方法的有效性和有效性。
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Circuit-level mismatch modelling and yield optimization for CMOS analog circuits
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniques with direct investigation of circuit behavior, and achieves model simplification and computational efficiency while ensuring sufficient accuracy. The circuit-level mismatch model can be used in performance characterization and yield estimation, both important in providing information for circuit reliability analysis. The proposed yield optimization technique consists of constructing and refining a yield model over the designable parameters, and ensures fast convergence to the global optimal design. The experimental results on two representative circuits confirm the efficiency and effectiveness of the proposed method.
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