{"title":"一种高速、低功耗、低电压的全差分CMOS采样保持电路","authors":"Tsung-Sum Lee, Chi-Chang Lu, S.H. Yu, J. Zhan","doi":"10.1109/ISCAS.2005.1465286","DOIUrl":null,"url":null,"abstract":"A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential double-sampled design relaxes the trade-off between sampling speed and the sampling precision. Simulation results are given to demonstrate the potential advantage of the new technique.","PeriodicalId":91083,"journal":{"name":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","volume":"95 1","pages":"3111-3114"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal\",\"authors\":\"Tsung-Sum Lee, Chi-Chang Lu, S.H. Yu, J. Zhan\",\"doi\":\"10.1109/ISCAS.2005.1465286\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential double-sampled design relaxes the trade-off between sampling speed and the sampling precision. Simulation results are given to demonstrate the potential advantage of the new technique.\",\"PeriodicalId\":91083,\"journal\":{\"name\":\"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems\",\"volume\":\"95 1\",\"pages\":\"3111-3114\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCAS.2005.1465286\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCAS.2005.1465286","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal
A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential double-sampled design relaxes the trade-off between sampling speed and the sampling precision. Simulation results are given to demonstrate the potential advantage of the new technique.
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