{"title":"基于FPGA的热感知低功耗通用异步收发器设计","authors":"Sunny Singh, A. Jain, A. Kaur, B. Pandey","doi":"10.1109/CICN.2014.198","DOIUrl":null,"url":null,"abstract":"Green communication is the latest research trend practiced by researcher in green computing and network communication. There is no extensive work in green network design and no work in thermal aware network equipment design. In order to fill this research gap, we are going to design thermal aware energy efficient Universal Asynchronous Receiver Transmitter (UART) that will create an avenue for thermal aware green communication. We had achieved 59.32% to 72.96% reduction when temperature varies from 15°C to 75°C and airflow is 250 Linear Feet Per Minute (LFM), and reduction is in range of 59.30% to 72.97%, when temperature varies from 15°C to 75°C and airflow is 500 LFM. This design is implemented on Virtex 6 Field programmable Gate Array (FPGA) using Verilog.","PeriodicalId":6487,"journal":{"name":"2014 International Conference on Computational Intelligence and Communication Networks","volume":"10 1","pages":"939-942"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Thermal Aware Low Power Universal Asynchronous Receiver Transmitter Design on FPGA\",\"authors\":\"Sunny Singh, A. Jain, A. Kaur, B. Pandey\",\"doi\":\"10.1109/CICN.2014.198\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Green communication is the latest research trend practiced by researcher in green computing and network communication. There is no extensive work in green network design and no work in thermal aware network equipment design. In order to fill this research gap, we are going to design thermal aware energy efficient Universal Asynchronous Receiver Transmitter (UART) that will create an avenue for thermal aware green communication. We had achieved 59.32% to 72.96% reduction when temperature varies from 15°C to 75°C and airflow is 250 Linear Feet Per Minute (LFM), and reduction is in range of 59.30% to 72.97%, when temperature varies from 15°C to 75°C and airflow is 500 LFM. This design is implemented on Virtex 6 Field programmable Gate Array (FPGA) using Verilog.\",\"PeriodicalId\":6487,\"journal\":{\"name\":\"2014 International Conference on Computational Intelligence and Communication Networks\",\"volume\":\"10 1\",\"pages\":\"939-942\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on Computational Intelligence and Communication Networks\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICN.2014.198\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on Computational Intelligence and Communication Networks","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICN.2014.198","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Thermal Aware Low Power Universal Asynchronous Receiver Transmitter Design on FPGA
Green communication is the latest research trend practiced by researcher in green computing and network communication. There is no extensive work in green network design and no work in thermal aware network equipment design. In order to fill this research gap, we are going to design thermal aware energy efficient Universal Asynchronous Receiver Transmitter (UART) that will create an avenue for thermal aware green communication. We had achieved 59.32% to 72.96% reduction when temperature varies from 15°C to 75°C and airflow is 250 Linear Feet Per Minute (LFM), and reduction is in range of 59.30% to 72.97%, when temperature varies from 15°C to 75°C and airflow is 500 LFM. This design is implemented on Virtex 6 Field programmable Gate Array (FPGA) using Verilog.