A study of 28nm LDMOS HCI improvement by layout optimization

LDMOS (lateral diffused MOS) is an important class of device finding applications in high voltage and smart power management due to their compatibility with the standard CMOS process. However, high operational drain voltage makes LDMOS devices highly vulnerable to the damage caused by hot-carrier injection (HCI). In this paper, the various layout parameters of NLDMOS with shallow trench isolation (STI) are systematically studied to check HCI performance using 28nm Poly/SiON logic process, including effective channel length (Lc), a drift region and poly gate overlap (Lp), a drift region and Pwell overlap/space (Lw) and STI width (Ls). Extensive TCAD simulations and experiments reveal that small Lp and large Lw overlap can greatly improve NLDMOS substrate current and HCI performance without any additional process step or process modification. The physical mechanism behinds the results should be that the impact ionization has been driven further away from the Si/SiO2 interface with a reduction in magnitude, which can improve substrate current and HCI performance.