用于电路仿真的超大规模集成电路互连片上电感建模和RLC提取

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852714

X. Qi, Gaofeng Wang, Zhiping Yu, R. Dutton, T. Young, N. Chang

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引用次数: 65

摘要

提出了从版图设计和工艺信息中获取三维几何图形的超大规模集成电路互连片上电感建模方法。推导出快速准确的电感估计解析公式，可用于电路仿真和整片提取筛选过程。电路仿真显示了关键的全局导线感应效应以及功率和地感应噪声。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation

On-chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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