Fast-transient asynchronous digital LDO with load regulation enhancement by soft multi-step switching and adaptive timing techniques in 65-nm CMOS

A digital low drop-out regulator (DLDO) load regulation enhancement technique which includes soft multi-step switching and adaptive timing is presented in this paper. As multi-step switching is widely used to balance the speed and resolution, a power-efficient method to improve the poor resolution during the switching between coarse- and finegrained regulations is in demand. The proposed technique, especially targeting at eliminating the undesired ripple voltage during multi-step switching, is implemented in a 65-nm asynchronous DLDO. This DLDO operates at an input voltage of 0.6V to 1V, and delivers a maximum of 500mA current with a 50mV drop-out voltage. In addition to responding to a nanoseconds' 500mA load current step and a 50mV per 10ns reference voltage change, an enhanced load regulation of 0.15mV/mA is achieved by adopting the proposed techniques.