使用组合逻辑实现AES s - box

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems Pub Date : 2008-05-18 DOI:10.1109/ISCAS.2008.4542162

Rashmi Ramesh Racch, P. Mohan

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引用次数: 13

摘要

本文考虑了两种适合FPGA解决方案的8位S-Box实现方法。这些使用(a)使用所有列的真值表的布尔简化来合成逻辑函数和(b)使用and和EXOR门合成ANF(代数范式)逻辑函数。给出了两种方案的硬件和计算时间评价。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Implementation of AES S-Boxes using combinational logic

In this paper, two approaches for implementation of the 8-bit S-Box suitable for FPGA based solutions are considered. These use (a) synthesis of the logic functions using Boolean simplification of the truth table of all the columns and (b) synthesis of the ANF (Algebraic Normal form) logic functions using AND and EXOR gates. The hardware and computation time evaluation for both the options are also presented.

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来源期刊

IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems

CiteScore

2.00

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0.00%

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