30 nm宽多层石墨烯- Ni双层互连的电学性能

T. Ishikura, A. Isobayashi, D. Nishide, B. Ito, Tatsuro Saito, Takashi Matsumoto, Y. Yamazaki, H. Miyazaki, Masahito Watanabe, N. Sakuma, A. Kajita, T. Sakai
{"title":"30 nm宽多层石墨烯- Ni双层互连的电学性能","authors":"T. Ishikura, A. Isobayashi, D. Nishide, B. Ito, Tatsuro Saito, Takashi Matsumoto, Y. Yamazaki, H. Miyazaki, Masahito Watanabe, N. Sakuma, A. Kajita, T. Sakai","doi":"10.1109/IITC-MAM.2015.7325591","DOIUrl":null,"url":null,"abstract":"We have fabricated the stacked interconnects of multi-layer graphene (MLG) and nickel (Ni) at the line width from 30 to 1000 nm in 300 mm wafer. MLG, which was grown by CVD process, was selectively deposited on Ni damascene interconnects by the catalytic reaction of Ni. MLG grown from C2H2 was composed of approximately 20 layers of graphene sheets and covered the overall surface of Ni interconnects. Two processes, one with the gas mixture of C2H2/Ar and the other with only Ar gas, were compared and short failure was observed at the comb structure specifically by the usage of C2H2 gas. Along with the failure analysis, this short failure was suggested to be caused by the unintended growth of carbon material from the Ni nanoparticle on the interconnects. An addition of ashing process improved the electrical performance with the minimum damage to MLG. At last, crystalline analysis of MLG suggests a necessity of a continuous process optimization of CVD process for positive influence on resistivity of the interconnects.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"65 1","pages":"321-324"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Electrical properties of 30 nm width bi-layer interconnects of multi layer graphene and Ni\",\"authors\":\"T. Ishikura, A. Isobayashi, D. Nishide, B. Ito, Tatsuro Saito, Takashi Matsumoto, Y. Yamazaki, H. Miyazaki, Masahito Watanabe, N. Sakuma, A. Kajita, T. Sakai\",\"doi\":\"10.1109/IITC-MAM.2015.7325591\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have fabricated the stacked interconnects of multi-layer graphene (MLG) and nickel (Ni) at the line width from 30 to 1000 nm in 300 mm wafer. MLG, which was grown by CVD process, was selectively deposited on Ni damascene interconnects by the catalytic reaction of Ni. MLG grown from C2H2 was composed of approximately 20 layers of graphene sheets and covered the overall surface of Ni interconnects. Two processes, one with the gas mixture of C2H2/Ar and the other with only Ar gas, were compared and short failure was observed at the comb structure specifically by the usage of C2H2 gas. Along with the failure analysis, this short failure was suggested to be caused by the unintended growth of carbon material from the Ni nanoparticle on the interconnects. An addition of ashing process improved the electrical performance with the minimum damage to MLG. At last, crystalline analysis of MLG suggests a necessity of a continuous process optimization of CVD process for positive influence on resistivity of the interconnects.\",\"PeriodicalId\":6514,\"journal\":{\"name\":\"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)\",\"volume\":\"65 1\",\"pages\":\"321-324\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IITC-MAM.2015.7325591\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC-MAM.2015.7325591","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

我们在300mm晶圆上制备了线宽为30 ~ 1000nm的多层石墨烯(MLG)与镍(Ni)的堆叠互连。CVD法制备的MLG通过Ni的催化反应选择性沉积在Ni - damascene互连层上。由C2H2生长的MLG由大约20层石墨烯片组成,覆盖了Ni互连的整个表面。对比了C2H2/Ar气体混合和Ar气体混合两种工艺,发现C2H2气体对梳状结构的破坏较短。随着失效分析,这种短失效被认为是由Ni纳米颗粒在互连上的碳材料意外生长引起的。灰化工艺的加入提高了电性能,同时对MLG的损伤最小。最后,对MLG的结晶分析表明,CVD工艺必须不断优化,才能对互连线的电阻率产生积极的影响。
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Electrical properties of 30 nm width bi-layer interconnects of multi layer graphene and Ni
We have fabricated the stacked interconnects of multi-layer graphene (MLG) and nickel (Ni) at the line width from 30 to 1000 nm in 300 mm wafer. MLG, which was grown by CVD process, was selectively deposited on Ni damascene interconnects by the catalytic reaction of Ni. MLG grown from C2H2 was composed of approximately 20 layers of graphene sheets and covered the overall surface of Ni interconnects. Two processes, one with the gas mixture of C2H2/Ar and the other with only Ar gas, were compared and short failure was observed at the comb structure specifically by the usage of C2H2 gas. Along with the failure analysis, this short failure was suggested to be caused by the unintended growth of carbon material from the Ni nanoparticle on the interconnects. An addition of ashing process improved the electrical performance with the minimum damage to MLG. At last, crystalline analysis of MLG suggests a necessity of a continuous process optimization of CVD process for positive influence on resistivity of the interconnects.
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