FeFET device structure design and analysis for low power circuit applications

This paper discusses the analysis of FeFET for low-power applications. The persistent scaling of computer capacity is necessary to handle the data's rapidly rising volume and complexity. CMOS technology's opportunities are shrinking as transistor size reduction approaches physical constraints. The new nanotechnologies have ability to replace the currently used CMOS and other technologies in energy-efficient computer devices. For information systems, ferroelectric FETs (FeFETs) are a potential candidate to continue improving power consumption. The FeFET analysis is carried out by evaluating drain current, transconductance, electric field, acceptor concentrations, and electric potential. Due to their energy, area efficiency and combined logic-memory functions, FeFETs, at the edge of semiconductor technology, are capable of meeting the requirements of integrated data computer applications. The proposed FeFET device has high ON current and small OFF current. The device exhibits a sub-threshold slope of 9.3 mV/dec, and the threshold voltage of 0.26 V. The proposed structure of FeFET is designed and simulated using the Silvaco TCAD tool. Proposed FeFET devices provides high-density and low-power circuit applications and would act as a promising candidate for the scientific and research community working in this area.